Error correction code interruption system

Details Error correction code interruption system Error correction code interruption system

1992-03-04

1992-10-20

Beausoliel, Robert W.

Excavating

H03M 1300

Patent

active

051576708

ABSTRACT:
Disclosed is a disk controller having an interruptable error correction code circuit for accumulating a remainder during the writing to or reading from data storage media in a disk storage device. An ECC clock latches each bit of data into the circuit when data is being transferred. The ECC clock is controlled by an ECC clock control circuit that monitors sector data and redundancy data transfers to interrupt the ECC clock when sector data transfer is suspended before redundancy data transfer is started. The ECC clock is then allowed to resume after the suspension is complete. Sector data transfer is suspended while the read/write head of the data storage device is passing a defect in the media of the storage device. Since the ECC clock control circuit interrupts the ECC clock while data transfer is suspended, the remainder accumulation will be interrupted while the defect is being passed. While the remainder accumulation is interrupted, the circuit acts as if data is not being transferred during this time. Thus, the defect can be skipped without the need to write redundancy data before the defect and then write additional fields of redundancy data until termination of the data field. ECC remainder accumulation is also halted during zone recording while the read/write head is passing sector positioning information. This allows data to be split between sectors without the need to add additional redundancy fields.

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