Error correction code and apparatus for the correction of differ

Communications: electrical – Digital comparator systems

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325 41, G06F 1112

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active

040357678

ABSTRACT:
This specification describes a convolutional code and apparatus for the correction of errors in differentially encoded quadrature phase shift keyed data (DQPSK). In each sequence of forty bits 24 are information bits and the remainder are parity bits. Two parity bits are generated for each three information bit set in the sequence in accordance with the following equations:

REFERENCES:
patent: 3891959 (1975-06-01), Tsuji et al.
patent: 3988677 (1976-10-01), Fletcher et al.
Forney, Jr. and Bower, A High-Speed Sequential Decoder: Prototype Design and Test, IEEE Transactions on Communication Technology, vol. Com-19, No. 5, Oct. 1971, pp. 821-835.
Chen and Rutledge, Error Correcting Codes for Satellite Communication Channels, IBM Journal of Research and Development, Mar. 1976, pp. 168-175.

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