Error correction check during write cycles

Details Error correction check during write cycles Error correction check during write cycles

1988-08-30

1990-05-15

Fleming, Michael R.

Excavating

371 402, G06F 1100

Patent

active

049264265

ABSTRACT:
An error correcting check of a memory system is provided when a memory in which the Dynamic Random Access Memory (DRAM) is of the type which has input lines that are directly coupled to its output lines. Utilizing this type of DRAM, the memory system employs controls, input, output and read circuitry to read bits out of the memory via the output circuitry and write circuitry to write bits into the memory via the input circuitry. An error checking and correction circuit is coupled to the output means which includes a check bit generator and a syndrome generator, and a control means energizes the error checking and correcting means during the write cycle, as well as the read cycle, so that the errors are detected during the write cycle as well as the read cycle. In this manner, errors which occur in circuitry other than the memory, which includes the memory driving and reading logic and also the check bit generator logic translators and syndrome generators, may be separately detected from memory errors.

REFERENCES:
patent: 4223382 (1980-09-01), Thorsrud
patent: 4506365 (1985-03-01), Collins
patent: 4531213 (1985-07-01), Scheuneman
patent: 4706248 (1987-11-01), Masaki
patent: 4780809 (1988-10-01), Woffinden

Affiliated with

Also associated with

Rating

Error correction check during write cycles does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Error correction check during write cycles, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Error correction check during write cycles will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-627681