Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2002-05-21
2004-06-08
Jeanglaude, Jean (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S163000
Reexamination Certificate
active
06747589
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to high speed, low-power SAR (successive approximation register) ADCs (analog-to-digital converters), and more particularly to an improved technique for operating an SAR ADC of generally conventional architecture to increase its conversion speed with little modification to its architecture or circuitry.
The basic conventional SAR ADC architecture is shown in
FIG. 1
, wherein a conventional CDAC (capacitive digital-to-analog converter) capacitor array
2
typically is connected to a charge summing conductor
7
A which is connected to the one of the inputs of a comparator
3
. The other input of comparator
3
is connected to a charge summing conductor
7
B of a conventional “dummy” CDAC capacitor array
4
. The output
4
of comparator
3
is connected to an input of a conventional SAR control logic circuit
5
, which produces a plurality of digital output signals Dout on a digital bus
6
that is coupled to transistor switches in CDAC capacitor array
2
. The transistor switches selectively couple the various capacitors in CDAC capacitor array
2
to a reference voltage conductor
9
conducting a reference voltage V
REF+
or to a reference voltage conductor
16
conducting a reference voltage V
REF−
, which typically is ground.
FIG. 2
shows a typical external reference voltage amplifier
8
which produces V
REF+
on conductor
9
within SAR ADC
1
of FIG.
1
. There is a substantial bonding wire inductance
10
A inside of an integrated circuit chip (indicated by the dashed line) on which the conventional SAR ADC
1
of
FIG. 1
is formed. Inductance
10
A is coupled between external conductor
9
A and an internal conductor
9
B conducting the internal value of V
REF+
which is applied by the transistor switches to the various capacitors of CDAC capacitor array
2
in accordance with digital signals Dout produced by SAR control logic
5
during the successive approximation testing/conversion operation. Reference numeral
13
A in
FIG. 2
represents series resistance of the transistor switch driving the CDAC, and conductor
9
and is shown as being lumped between node
9
and the output of an internal buffer
11
.
Reference numeral
12
in
FIG. 2
designates the widely variable capacitance C
CDAC
of the portion of CDAC capacitor array
2
which effectively “loads” reference voltage amplifier
8
during the successive approximation process. If internal buffer
11
is omitted, then waveform V
9A
in
FIG. 2
indicates “ringing” of voltage that would be caused by bonding wire inductance
10
A on conductor
9
B when the CDAC array capacitance
12
varies suddenly due to switching that occurs in response to the digital signals
6
to establish the successive mid-range voltages needed for testing/conversion of each bit of the output word Dout.
Therefore, in the prior art it is usually necessary to provide above mentioned internal buffer circuit
11
to isolate the inductance
10
A from the variable CDAC array capacitance
12
to avoid the kind of ringing indicated by waveform V
9A
. For high resolution ADCs, the CDAC capacitance has to be large, to achieve good noise and matching performance. Therefore, the switching load on the reference buffer is high for high resolution devices. Also, the speed at which the conversion is done puts a constraint on the settling time of the buffer. All these factors together increase the power consumption of the buffer
11
. Undesirably, such an internal buffer
11
occupies a substantial amount of chip area and consumes a substantial amount of power.
One of the main drawbacks of high speed SAR ADCs that utilize internal CDACs (capacitive digital-to-analog converters) is that the external reference voltage amplifier driving the CDAC is subjected to the above mentioned widely changing capacitive load, depending on the value of the digital output word being generated to represent the analog input signal Vin. Consequently, if N is large, e.g., 16 bits or more, a large amount of time has to be allowed for the reference voltage amplifier
8
to settle to an accuracy corresponding to the N bit output word being produced.
FIG. 3
shows more details of CDAC capacitor array
2
, wherein reference numeral
14
designates a plurality of binarily weighted CDAC array capacitors each having an upper terminal connected to charge summing conductor
7
A and a lower terminal selectively coupled by a transistor switch circuit
15
to either V
REF+
or V
REF−
in response to the digital control signals
6
during the successive approximation bit testing/conversion procedure.
In the conventional SAR ADC
1
of
FIG. 1
, an analog input Vin=Vin±Vin− is applied between an input conductor
17
A of CDAC capacitor array
2
and an input conductor
17
B of dummy CDAC capacitor array
4
. Vin+ and Vin− are sampled by means of input coupling capacitors in main CDAC array
2
and dummy CDAC array
4
during a sampling phase. At the end of the sampling phase, a conventional binary search algorithm is performed in response to the output of comparator
3
to establish a binary mid-range value for the output bit currently being tested/converted. Comparator
3
in effect compares the sampled analog input voltage to the present value of the binary mid-range value established in main CDAC array
2
, and assigns a binary value of “1” to the bit presently being tested if the sampled analog input voltage exceeds the binary mid-range value, and otherwise assigns a binary “0” to the bit being tested/converted. As the conventional conversion process proceeds, it includes progressively testing and assigning “1” or “0” values to the output bits, one at a time, beginning with the MSB (most significant bit), to produce the output word Dout.
Each bit of the digital output word Dout, beginning with the MSB (most significant bit), is tested sequentially by comparator
3
to determine if that bit should be a “1” or a “0”. For an N bit accuracy of the ADC, the comparator should be able to resolve the difference of (Vref/2
N
) at its inputs. If N is increased, the comparator either (1) requires more time to settle, or (2) requires more bandwidth and consequently consumes more power if no more time is allowed for settling in order to resolve the more accurate bit testing decisions necessitated by the increasing of N.
In a typical SAR ADC, the analog to digital conversion proceeds one bit at a time until all of the bits of the digital output word are resolved, i.e., converted. All of the bits are processed at the full accuracy level required for an N-bit digital output word, so an equal amount of time is required to resolve each of the N bits of the output word Dout. Therefore, the amount of time required for a typical analog-to-digital conversion by an SAR ADC is:
Tcycle=Tsample+N*Tclock,
where Tclock is the time required for resolving any one of the N bits of the output word.
The design of high-speed, high-resolution SAR ADCs is substantially limited by the speed of the comparator
3
, by the bandwidth/power/settling time of the external reference voltage amplifier
8
, and the internal settling time of the charge summing conductor
7
A of the CDAC array
2
. The higher the resolution of the SAR ADC, the more stringent the limitations on the amount of noise that can be present in the comparator, and the higher the amount of CDAC switching capacitance that the reference voltage amplifier must drive as it settles. The higher the desired speed of analog-to-digital conversion, the higher the speed, bandwidth and power consumption of comparator
3
must be, and the less time is available during which the voltage reference amplifier
8
must settle to the required accuracy level during the successive approximation testing/conversion of each bit. The amount of time required for the internal CDAC charge summing conductor
7
A to settle to the required accuracy level includes two components, including (1) an RC time constant which determines the amount of time requi
Godbole Kiran M.
Srinivasan Chakravarthy
Brady W. James
Jeanglaude Jean
Swayze, Jr. W. Daniel
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
LandOfFree
Error correction architecture to increase speed and relax... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Error correction architecture to increase speed and relax..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Error correction architecture to increase speed and relax... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3305820