Error correction architecture for pipeline analog to digital con

Details Error correction architecture for pipeline analog to digital con Error correction architecture for pipeline analog to digital con

1997-11-20

2000-09-26

Tokar, Michael

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

341118, H03M 138

Patent

active

061248207

ABSTRACT:
A pipeline analog to digital converter architecture includes at least two error correction stages, one such error correction stage at the end of the pipeline architecture such that power savings and silicon area optimization are achieved by tailoring the performance of the pipeline stages towards the end of the pipeline architecture. The other error correction stages are placed with respect to the overall design sensitivities. The design according to the present invention is applicable to a broad class of pipeline architectures including multi-bit stages in the pipeline architecture.

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"A 12-b 600 ks/s Digitally Self-Calibrated Pipelined Algorithmic ADC", IEEE Journal of Solid-State Circuits, Apr. 1994.
"A 15-b 1-Msample/s Digitally Self-Calibrated Pipeline ADC", IEEE Journal of Solid-State Circuits, Dec. 1993.
"Clever Designs Spawn 40-MHz/10-Bit/0.2-W ADCs", Electronic Design, Jan. 1994.

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