Error correction and detection systems

Details Error correction and detection systems Error correction and detection systems

1979-10-12

1981-10-20

Atkinson, Charles E.

Excavating

371 38, G06F 1110

Patent

active

042964946

ABSTRACT:
In a system which employs SEC-DED codes constituted by data bits added to redundant bits and is capable of detecting and correcting a single bit error while detecting a double or more bit error, detection is made on miscorrection ascribable to a triple bit error. When a single bit error is detected by an error detecting and correcting circuit in the SEC-DED code read out from a memory, all the corrected data bits are inverted in state and rewritten in the memory after having been added to new redundant bits. Subsequently, the data bits together with the redundant bits are read out from the memory and supplied to the error detecting and correcting circuit. The data bits obtained from the error detecting and correcting circuit are compared with the corrected and inverted data bits available before being written in the memory, to thereby determine the presence of an error encompassing more than (m+1) bits on the basis of the result of comparison.

REFERENCES:
patent: 3273120 (1966-09-01), Dustin et al.
patent: 3949208 (1976-04-01), Carter
patent: 4037091 (1977-07-01), Beuscher
patent: 4045779 (1977-08-01), Markle
patent: 4175692 (1979-11-01), Watanabe
Bachman and Dobrzynski, Multiple Error Correction, IBM Technical Disclosure Bulletin, vol. 13, No. 8, Jan. 1971, p. 2190.

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