Error correction and detection apparatus and method

Details Error correction and detection apparatus and method Error correction and detection apparatus and method

1988-12-29

1990-12-18

Atkinson, Charles E.

Excavating

G06F 1110

Patent

active

049791745

ABSTRACT:
A decoder is arranged to operate as a single-bit error correction circuit (ECC) and as a multiple-bit error detection circuit (EDC). The decoder starts and remains in the ECC state as long as no errors are detected in a received data message. When an error is detected or corrected in a received data message, the decoder switches to the EDC state where it remains as long as errors are detected in the received data message. When no errors are detected in the received data message, the decoder switches back to the ECC state. In a generalized multistate decoder, switching occurs from one state to another state, each state having a different error correcting capability, in response to a predetermined number of errors corrected or detected in the received data.

REFERENCES:
patent: 3078443 (1963-02-01), Rose
patent: 4047151 (1977-09-01), Rudbeck et al.
patent: 4336611 (1982-06-01), Bernhardt et al.
patent: 4397022 (1983-08-01), Weng et al.
patent: 4410988 (1983-10-01), Suelflow et al.
patent: 4592054 (1986-05-01), Namekawa et al.
patent: 4701923 (1987-10-01), Fukasawa et al.
patent: 4703486 (1987-10-01), Bemis

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