1981-04-24
1983-07-19
Atkinson, Charles E.
Excavating
364900, 371 10, 371 13, G06F 1110, G11C 2900
Patent
active
043947638
DESCRIPTION:
BRIEF SUMMARY
DESCRIPTION
The present invention relates to an error-correcting system and, more particularly, relates to an error-correcting system for correcting errors occurring in a main memory of a computer system.
In recent years, most memories are fabricated by using semiconductor memory devices, so that memories having very large capacities can easily be obtained and, also, very low price memories can be realized. Generally, the larger the capacities of individual memories become, the more errors occur and accordingly, in such very large capacity memories, it is very important to supervise the occurrence of errors produced in the memories. In order to supervise the occurrence of errors, an ECC circuit or Error Correction Code logic circuit has been proposed. The ECC logic circuit usually cooperates with the main memory of the computer system, so as to automatically correct n(n is positive integer)-bit errors occurring in the memory and, also, to detect an occurrence of n+1-bit errors in the memory.
At the present time, extremely large capacity memories are about to be put to practical use. For example, in a RAM (Random Access Memory), the bit density thereof is being advanced from 64 K(Kilo)bits to 256 Kbits. Accordingly, the 256 Kbits RAM will soon be widely put to practical use.
However, when the bit density increases to such a very high bit density as, for example 256 Kbits, a certain problem arises. The problem is the occurrence of a so-called soft error. The term "soft error" is a recent term, because the phenomenon of soft errors was discovered only a few years ago. The reason such a soft error phenomenon is created is now considered and understood to be as follows. When the bit density of the memory is increased, the memory must be fabricated by using very fine conductors distributed on great number of memory cells. Accordingly, electric charges, stored in parasitic capacitors distributed along said very fine conductors, become very small. Such very small electric charges are liable to be dissipated by external forces due to, for example, an application of radio active rays, above all alpha rays, to the high density memory cells. That is, if alpha rays pass through one of the memory cells, the logic of the data (electric charges) stored in the memory cell, through which the alpha rays have passed, may easily be inverted into the opposite data logic. Thus, the above mentioned soft errors often occur in a high density memory device. It should be noted that a soft error is a single-bit error which occurs at random in the memory device and, also, does not occur repeatedly at the same memory cell.
Although the term "soft error" is the recent term, the term "hard error" is already widely known. A hard error is created due to an occurrence of trouble, breakage or wearing out of the memory device. Such hard error occurs repeatedly in the same memory cell and, also, the logic of the data stored in the memory cell having the hard error is fixed to be either the logic "1" or logic "0". We know, through experience, that the hard error may occur with a probability of 200 through 250 FIT, which means that any hard error occurs with a probability of ##EQU1## per hour. It is a well known fact that, usually, some of the hard errors, for example, about 30% of the hard errors among all the errors occurring during a unit of time, are hard errors that are spread over bits of a plurality of word addresses in one memory device or over a bit of all the word addresses contained in one memory device.
Further, it is important to know that, in the memory device having an extremely high bit density, for example 256 Kbits, the frequency of occurrence of the soft errors may be much higher than the frequency of occurrence of the hard errors, by more than one thousand times. Consequently, the following problems will be produced.
(A) Firstly, although certain fixed data have been written in respective memory cells through write operations, soft errors may occur at two bit positions within each of some words as time elapses after said writ
REFERENCES:
patent: 3917933 (1975-11-01), Scheuneman et al.
patent: 3949208 (1976-04-01), Carter
patent: 4175692 (1979-11-01), Watanabe
patent: 4255808 (1981-03-01), Schaber
patent: 4296494 (1981-10-01), Ishikawa et al.
patent: 4319356 (1982-03-01), Kocol et al.
patent: 4359771 (1982-11-01), Johnson et al.
Nagano Genzo
Takahashi Masao
Atkinson Charles E.
Fujitsu Limited
LandOfFree
Error-correcting system does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Error-correcting system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Error-correcting system will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-755291