Error correcting system

Details Error correcting system Error correcting system

1985-08-20

1987-12-29

Smith, Jerry

Excavating

G06F 1110

Patent

active

047165669

ABSTRACT:
A first error correcting code and a first parity bit associated with a data word are transmitted to an external circuit. Through the external circuit the data word, the first error correcting code and the first parity bit are received and a second error correcting code and a second parity bit associated with the received data word are generated based upon the received data word. An error correction signal is generated when difference between the first and second error correcting codes is found. A parity error signal is generated when the first and second parity bits are different. The error of the received data word is corrected by the error correction circuit only in a case that the error correction signal and the parity error signal are generated. The error correction circuit outputs the received data word without error correction in other cases.

REFERENCES:
patent: 3573728 (1971-04-01), Kolankowsky
patent: 4417339 (1983-11-01), Cantarella
patent: 4520481 (1985-05-01), Israel
patent: 4523314 (1985-06-01), Burns
patent: 4531213 (1985-06-01), Scheuneman
R. J. Cooper, "Diagnostic Error-Forcing Circuit", IBM TDB, vol. 19, No. 5, 10/1976, pp. 1833-1834.

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