Error correcting network

Details Error correcting network Error correcting network

1981-02-09

1983-09-13

Atkinson, Charles E.

Excavating

371 38, G06F 1110, G11C 2900

Patent

active

044046731

ABSTRACT:
An error correcting network adapted for encoding and decoding data transferred to and from a bubble memory has parallel linear encoder/decoder circuits. An error syndrome generated in response to a parity error in an initial read operation is used by one encoder/decoder circuit for correcting the parity error during a subsequent reread of the data. The error syndrome is also stored in a latch for comparison with a second error syndrome generated in response to the data during the reread operation. A true comparison between the two error syndromes verifies that that data has not changed between the two read operations due to a soft error and that the error correction of the first encoder/decoder circuit is valid.

REFERENCES:
patent: 3582880 (1971-06-01), Beausoleil
patent: 4037091 (1977-07-01), Beuscher
patent: 4216541 (1980-08-01), Clover et al.
patent: 4319356 (1982-03-01), Kocol et al.
P. W. Woo, Error Correction Upon Digital Transmission from a Digital Recording Device, IBM Tech. Discl. Bulletin, vol. 9, No. 9, Feb. 1967, pp. 1107-1109.
Gourneau and Hinkel, Error Correction as an Extension of Error Recovery on Information Strings, IBM Tech. Discl. Bulletin, vol. 24, No. 1B, Jun. 1981, pp. 651-652.

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