Error correcting encoder/decoder for a digital transmission inst

Details Error correcting encoder/decoder for a digital transmission inst Error correcting encoder/decoder for a digital transmission inst

1990-02-26

1992-06-23

Beausoliel, Robert W.

Excavating

371 376, G06F 1110

Patent

active

051249928

ABSTRACT:
An encoder and decoder for use with a Wyner-Ash code whose memory order m is not less than six. Both the encoder and decoder operate in series by means of six shift registers connected in series, thereby making it possible to calculate a check bit on encoding in parallel by means of respective exclusive OR circuits, and consequently also making it possible to calculate a syndrome bit on decoding by a complementary exclusive OR circuit. Successive syndrome bits specify the position of an error in a received message, and the error is then corrected in the last shift register of the decoder.

REFERENCES:
patent: 3593282 (1971-07-01), Tong
patent: 3842400 (1974-10-01), Liefeld et al.
patent: 5022031 (1991-06-01), Baggen
IEE Proceedings F. Communications, Radar & Signal, vol. 132, No. 2, Apr. 1985, Stevenage GB, pp. 77-83; I. S. Reed & T. K. Truong: "Error-Treillis Syndrome Decoding Techniques for Convolutional Codes".
IEEE Transactions on Information Theory, vol. IT-9, Jul. 1963, New York USA, pp. 143-156; A. D. Syner & R. B. Ash: "Analysis of Recurrent Codes".
IEEE Transactions on Computers, vol. C-35, No. 9, Sep. 1986, New York, USA, pp. 781-789; I. S. Reed et al.: "The VLSI Design of an Error Trellis Syndrome Decoder for Certain Convolutional Codes".
IEEE Journal of Selected Areas in Communction, vol. 6, No. 3, Apr. 1988, New York, USA, pp. 547-557; D. Haccoun et al.: "New Architechtures For Fast Convolutional Encoders and Threshold Decoders."

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