Error correcting decoder

Details Error correcting decoder Error correcting decoder

1995-05-25

1998-04-28

Elmore, Reba I.

Excavating

H03M 1300

Patent

active

057455066

ABSTRACT:
An error correcting decoder includes a flag memory (20) which stores a flag indicative of a success of an error correction for a bit. When a column direction error correction is to be performed, if a flag for a bit indicates a success, no error correction is performed for the bit. That is, an output of a majority logic circuit (78) is forcedly made invalid. In performing the column direction error correction, if the number of success packets in a first-time row direction error correction is smaller than a predetermined value and if the number of bits corrected by the column direction error correction becomes equal to or larger than a predetermined number, it is deemed as that the column direction error correction is unsuccessful. In performing a second-time row direction error correction, when a threshold value is equal to or larger than a predetermined value, the majority logic circuit determines with referring to a result of the column direction error correction, but without referring to the result when the threshold value is smaller than the predetermined value.

REFERENCES:
patent: 4404674 (1983-09-01), Rhodes
patent: 4630271 (1986-12-01), Yamada
patent: 4660199 (1987-04-01), Maeda et al.

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