Error correcting code system

Details Error correcting code system Error correcting code system

1980-06-30

1982-06-08

Atkinson, Charles E.

Excavating

371 37, G06F 1110

Patent

active

043343090

ABSTRACT:
An error correcting code mechanism for SEC-DED (16, 21) or (8, 12) code to correct data bit errors caused by alpha particle impingement into high density storage units. The data word is read into and out of a high density storage unit and generated check bits are stored in low density storage immune to alpha particle radiation. Data bits and check bits, addressed in parallel are read out to error detecting and correcting circuits to determine the existence of an error only in a data bit and correct the state of the erroneous bit. The number of check bits and required parity and checking circuitry is reduced since no error checking of check bits, presumed to always be correct because of the use of low density storage occurs.

REFERENCES:
patent: 3982226 (1976-09-01), Bunker et al.
patent: 3988580 (1976-10-01), Warman et al.
patent: 4031374 (1977-06-01), Groudan et al.
Conzola and Tung, Error Correction Without Speed Degradation, IBM Technical Disclosure Bulletin, vol. 10, No. 8, Jan. 1968, pp. 1275-1276.

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