Error-correcting circuit having a reduced syndrome word

Details Error-correcting circuit having a reduced syndrome word Error-correcting circuit having a reduced syndrome word

1984-12-26

1987-03-10

Atkinson, Charles E.

Excavating

371 38, G06F 1110

Patent

active

046495401

ABSTRACT:
An error-correction circuit for correcting up to one error in an M-bit data field having the conventional number K parity bits associated with it uses a syndrome word having K-1 bits. The data elements are ordered sequentially and the K-1 bit syndrome word points to errors in the data only, not to errors in the parity bits. One of the data addresses in the field is reserved as a no-error flag and a Kth parity check bit associated with the syndrome word flags an error in the parity bits.

REFERENCES:
patent: 3825893 (1974-07-01), Bossen et al.
patent: 4345328 (1982-08-01), White
patent: 4359772 (1982-11-01), Patel
patent: 4523314 (1985-06-01), Burns et al.
patent: 4561095 (1985-12-01), Khan

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