Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2000-12-07
2001-12-18
Phan, Trong (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
Reexamination Certificate
active
06331948
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-350655, filed Dec. 9, 1999; the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an error correcting circuit for making efficient error correction and a nonvolatile semiconductor memory device incorporating the same error correcting circuit. More particularly, the present invention relates to technology of the nonvolatile semiconductor device incorporating the error correcting circuit for achieving efficient error correction and reduction of power consumption.
2. Background Art
A conventional nonvolatile memory such as a flash memory loaded on a high reliability apparatus has a problem in defective rate (failure rate). To reduce this error rate, a nonvolatile memory having error correcting function has been developed for high reliability applications.
According to an error correction method by this error correcting function disclosed in, for example, Japanese Patent Application Laid-Open No. H5-002898, the error correction is carried out by adding plural redundant bits to information bits to be accessed so as to obtain hamming code. If error correction for 1 bit is carried out with respect to N-bit information bits, X-bit error correction code (that is, check bit) is necessary and the quantity of the check bit is obtained according to (N+X)+1≦2
x
. For example if error correction of 1 bit is carried out for 32-bit information bits, 6-bit error correction code (check bit) is necessary from the above described equation. An inspection bit generation matrix for generating this check bit is determined by a matrix of 6 rows×32 columns shown in the following equation 1. The check bit (P) is obtained by logical operation shown in the equation 2 based on the check bit generation matrix (A) and 32-bit information bits (D
0
-D
31
).
A
=
[
a
(
0
,
0
)
a
(
0
,
1
)
⋯
a
(
0
,
31
)
a
(
1
,
0
)
⋮
a
(
2
,
0
)
⋮
a
(
3
,
0
)
⋮
a
(
4
,
0
)
⋮
a
(
5
,
0
)
⋯
⋯
a
(
5
,
31
)
]
[
equation
1
]
P
=
A
*
[
D0
⋮
D31
]
[
equation
2
]
On the other hand, when detecting an error, a matrix of 6 rows×38 columns (B) shown in the following equation 3 and 32-bit information bits (D
0
-D
31
) containing 6-bit check bits (P
0
-P
5
) are logically computed as shown in the following equation 4. As a result, a position of the error bit can be specified.
B
=
[
a
(
0
,
0
)
a
(
0
,
1
)
⋯
a
(
0
,
31
)
b
(
0
,
32
)
⋯
b
(
0
,
37
)
a
(
1
,
0
)
⋮
⋮
a
(
2
,
0
)
⋮
⋮
a
(
3
,
0
)
⋮
⋮
a
(
4
,
0
)
⋮
⋮
a
(
5
,
0
)
⋯
⋯
a
(
5
,
31
)
b
(
5
,
32
)
⋯
b
(
5
,
37
)
]
[
equation
3
]
X
=
B
*
[
D0
⋮
D31
P0
⋮
P5
]
[
equation
4
]
The conventional error correcting circuit (hereinafter referred to as “ECC circuit: Error Checking and Correcting Circuit”) having such a function comprises a check bit generation circuit for generating a check bit for rewrite data at the time of write, a syndrome calculating circuit for determining presence or absence of an error by the information bit and check bit at the time of readout and a correction circuit for correcting by inverting the information bit if there is found an error.
Next, an access operation of the nonvolatile memory (for example, FLASH EEPROM: Electrically Erasable and Programmable Read Only Memory) for erasing in the unit of plural addresses (block, that is, unit of certain amount of bits) will be described.
First, in the readout operation, 32-bit information bits selected for an address inputted from outside and accompanying 6-bit check bits are accessed at the same time and read out through a readout circuit. A readout result is inputted to the syndrome calculating circuit and the logical operation shown in the previous equation 4 is carried out to detect whether or not there is an error in the read out information bits. If an error is detected in the information bits as a result of the syndrome computation, the information bit is corrected by the correction circuit based on that detection result and outputted.
Second, in a write operation, the 6-bit check bits shown in the previous equation 2 is generated in the check bit generation circuit for 32-bit write data inputted from outside. The write data for an address is 38 bits while 32-bit information bits and 6-bit check bits are held separately.
Third, in an erasing operation, the information bit and check bit are erased at the same time. If each bit value is assumed to be “1” at the time of erasing, all values of the information bits and check bits are “1”. If all the information bits are “1” and all the check bits are “1” as a result of reading out respective bits, all bits read out become “1”, which means that no error is detected in the syndrome computation.
Although the matrix (B) shown in the previous equation 3 at the time of syndrome computation can be set arbitrarily, conflict may occur in the aforementioned erasing condition. If data is inverted so that all erased data becomes “0” in order to avoid this conflict, the result of syndrome computation becomes “0” even if any matrix is set up, so that the conflict can be avoided.
On the other hand, in some nonvolatile memory such as a flash EEPROM for carrying out intelligent control, write is carried out corresponding to all addresses prior to erasing operation so as to equalize a threshold of cell before erasing and by carrying out the erasing operation after that, a distribution of the thresholds after the erasing is narrowed.
According to this method, in write operation prior to the erasing, it is necessary to write “1” check bit into all “1” information bits and then, “0” check bit into all “0” information bits. Therefore, a check bit generation matrix for generating the “1” check bit for all the “1” information bits and the “0” check bit for all the “0” information bits is necessary.
On the other hand, because, in normal write operation, the check bit generation matrix is set up arbitrarily, the check bits do not become “1” for all the “1” information bits. Therefore, the check bit generation matrix used for the normal write operation cannot be used for a write operation before erasing. Thus, if a system which writes to all addresses prior to the aforementioned erasing is employed, algorithm of erasing operation including the write operation prior to the erasing operation have to be changed in case where such a system is not employed.
On the other hand, in the aforementioned erasing operation, the information bit and check bit are erased at the same time in the nonvolatile memory such as the flash memory EEPROM having an ECC circuit. Thus, current at the time of the erasing operation increases so that power consumption increases. Further, because the information bit and check bit are read out at the same time, current at the time of readout increases so that power consumption increases.
As described above, in the conventional nonvolatile memory having the ECC circuit which employs a system in which the distribution of the threshold is adjusted after the erasing, the same check bit generation matrix cannot be used for the normal write operation and the write operation prior to the erasing. For the reason, there is generated such a problem that the algorithm of the write operation becomes complicated.
Further, because the information bit and check bit are erased and read out at the same time, there is another problem that power consumption increases.
SUMMARY OF THE INVENTION
The present invention has been achieved to s
Kasai Nozomi
Kasai Takamichi
Gray Cary Ware & Freidenrich LLP
Kabushiki Kaisha Toshiba
Phan Trong
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