Error correcting circuit arrangement using cube circuits

Details Error correcting circuit arrangement using cube circuits Error correcting circuit arrangement using cube circuits

1976-12-13

1977-12-20

Smith, Jerry

Communications: electrical

Digital comparator systems

G06F 1112

Patent

active

040644839

ABSTRACT:
An error correcting circuit utilizing a cube circuit for correcting errors in data having n+1 bits in accordance with the syndromes S.sub.1 and S.sub.3 from a check matrix H. The circuit comprises a generator for generating syndromes S.sub.1 and S.sub.3, means for providing (S.sub.1 -a.sub.i) based on the modulo 2 calculation for the i.sub.th line vector ##EQU1## OF THE CHECK MATRIX H corresponding to each data bit d.sub.1, means for multiplying (S.sub.1 -a.sub.i) three times, check means for checking the coincidence between (S.sub.1 -a.sub.i) and (S.sub.3 -a.sub.i.sup.3), and an inverting means for inverting the d.sub.i bit when the coincidence is detected.
In the present invention, by utilizing a cube circuit the check circuit can be simplified.

REFERENCES:
patent: 3278729 (1966-10-01), Chien
patent: 3685014 (1972-08-01), Hsiao et al.
patent: 3714629 (1973-01-01), Hong et al.
patent: 4030067 (1977-06-01), Howell et al.

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