Error-correcting apparatus

Excavating

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371 376, G06F 1110

Patent

active

055047580

ABSTRACT:
In an error-correcting apparatus for correcting errors included in reproduced data which are stored in a RAM, a syndrome generation circuit, a polynomial calculation circuit for calculating an error position polynomial and an error value polynomial, and a position calculation circuit for calculating an error position are operated in parallel. A divider section of the error-correcting apparatus has a divider for performing the division of highest-degree coefficients of two polynomials, a multiplier for multiplying the coefficient of the polynomial set in the divisor side of the divider by the output of the divider, and an adder for adding the output of the multiplier and the coefficient of the polynomial set in the dividend side of the divider. The divider section executes the division over a Galois field while sequentially shifting the contents of registers which store the coefficient data of the dividend polynomial.

REFERENCES:
patent: 4597083 (1986-06-01), Stenerson
patent: 4747103 (1988-05-01), Iwamura et al.
patent: 5099483 (1992-05-01), Kadokawa
Code Theory, by Hideki Imai, pp. 115-115, 165-166, Electronic Data Transmssion Society.
"An Experimental Home-Use Digital VCR with Three Dimensional DCT and Superimposed Error Correction Coding", IEEE Transactions on Consumer Electronics, vol. 37, No. 3, Aug. 1991.
Controller for Optical Disk Apparatus: Real-time Error Correction Conducting Hardware Processing, Nikkei Electronics, pp. 167-177, May 1, 1989.

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