Error-correctible bit-organized RAM system

Details Error-correctible bit-organized RAM system Error-correctible bit-organized RAM system

1975-11-14

1977-02-01

Fears, Terrell W.

Communications: electrical

Digital comparator systems

340173, 340 66, 340173AM, G11C 1140

Patent

active

040064670

ABSTRACT:
A memory organization system is disclosed which comprises an improved, bit-organized RAM system. The invention substantially limits errors within the RAM system such that they are error-correctible by existing error detection and correction means. Commonly available RAMs are organized on a logic board such that each bit of a word being addressed is provided by a different RAM chip and is driven by a distinct driver. In this manner a malfunction in either a chip or a driver circuit results in only a one-bit error per word and overall system performance is also improved.

REFERENCES:
patent: 3365707 (1968-01-01), Mayhew
patent: 3893088 (1975-07-01), Bell

Affiliated with

Also associated with

Rating

Error-correctible bit-organized RAM system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Error-correctible bit-organized RAM system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Error-correctible bit-organized RAM system will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1094104