Error control method and apparatus

Details Error control method and apparatus Error control method and apparatus

1986-12-10

1989-02-14

Atkinson, Charles E.

Excavating

G06F 1110

Patent

active

048051730

ABSTRACT:
A method and apparatus are described for error control and correction which operates across multiple processors and multiple computer memories. In accordance with the invention, data signals from a plurality of processors are applied in parallel to a syndrome generator that generates a syndrome related to such signals. The syndrome is then stored in parallel in a plurality of read/write memories at the same address as the data signals from which the syndrome was generated. When the data signals are read from memory, they are again provided to the syndrome generator which again generates a new syndrome. At the same time the old syndrome signals stored at the same memory addresses are read from memory and compared with the new syndrome. If the two syndromes are the same, there is no error and the data signals are valid. If the syndromes are different, a syndrome decoder determines if sufficient information is available in the syndrome signals to correct the error and does so if it can.

REFERENCES:
patent: 4319356 (1982-03-01), Kocol et al.
patent: 4345328 (1982-08-01), White
patent: 4561095 (1985-12-01), Khan
patent: 4593393 (1986-06-01), Mead et al.
patent: 4646304 (1987-02-01), Fossati et al.

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