Error control coding arrangement for digital communications syst

Details Error control coding arrangement for digital communications syst Error control coding arrangement for digital communications syst

1993-12-23

1995-01-24

Chin, Stephen

Pulse or digital communications

Repeaters

Testing

375 27, 375 38, 371 43, H04L 2700

Patent

active

053848098

ABSTRACT:
A serial-parallel converter is arranged to convert an information sequence into a plurality of bit sequences. Two convolutional encoders are provided which respectively receive bit sequences from the serial-parallel converter. Each of the two convolutional encoders outputs first and second bit sequences. First parallel-serial converter receives the first bit sequences and converts them into third bit sequence, while second parallel-serial converter receives the second bit sequences and converts them into fourth bit sequence. The third and fourth bit sequences are used to modulate two carriers with a phase difference of .pi./2 radians.

REFERENCES:
patent: 4462101 (1984-07-01), Yasuda et al.
patent: 4489418 (1984-12-01), Mazo
patent: 4534040 (1985-08-01), Thapar
patent: 4581748 (1986-04-01), Sasaki et al.
patent: 4873703 (1989-10-01), Tretter
IEEE Proceedings F. Communications, Radar & 1-3 Signal Processing vol. 134, No. 1, pp. 43-52.

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