Error control apparatus and method for channel equalizer

Details Error control apparatus and method for channel equalizer Error control apparatus and method for channel equalizer

2006-06-27

2006-06-27

Corrielus, Jean (Department: 2637)

Pulse or digital communications

Equalizers

Automatic

C375S234000, C375S235000

Reexamination Certificate

active

07068714

ABSTRACT:
A channel equalizer includes an equalizer filter for correcting an error upon receipt of a signal transmitted by a sending end, a DD slicer for calculating a first error upon receipt of the corrected signal from the equalizer filter, a Sato slicer for calculating a second error upon receipt of the corrected signal from the equalizer filter, and a DD error size calculation unit for taking the absolute value of the real part and imaginary part of the first error calculated from the DD slicer and summing these absolute values.

REFERENCES:
patent: 5692011 (1997-11-01), Nobakht et al.
patent: 5956328 (1999-09-01), Sato
patent: 6188722 (2001-02-01), Velez et al.
patent: 6421378 (2002-07-01), Fukuoka et al.
patent: 6426680 (2002-07-01), Duncan et al.
patent: 6426972 (2002-07-01), Endres et al.
patent: 6496229 (2002-12-01), Limberg
patent: 6505222 (2003-01-01), Davis et al.
patent: RE38456 (2004-03-01), Patel et al.

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