Error connection device for parity protected memory systems

Details Error connection device for parity protected memory systems Error connection device for parity protected memory systems

1988-06-17

1990-07-17

Fleming, Michael R.

Excavating

371 211, 365200, G06F 1114

Patent

active

049425757

ABSTRACT:
The use of a redundant memory subsystem, memory flow control, and a method of copying (srubbing) data from the location of one memory subsystem to the corresponding location in the other memory subsystem provides correction of soft errors in a parity protected memory system without degrading the performance of the memory system except when an error occurs. A copy of the correct data is also provided to the memory system when a location in either of the memory subsystems experiences a hard error.

REFERENCES:
patent: 4654847 (1987-03-01), Dutton
patent: 4656610 (1987-04-01), Yoshida
patent: 4688219 (1987-08-01), Takemae
patent: 4752914 (1988-06-01), Nakano
patent: 4807191 (1989-02-01), Flannagan

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