Error checking and correcting for read-modified-write operations

Details Error checking and correcting for read-modified-write operations Error checking and correcting for read-modified-write operations

1987-12-28

1989-11-28

Smith, Jerry

Excavating

G06F 1100

Patent

active

048842710

ABSTRACT:
Error detection and correction logic is interposed between a 16-bit CPU and a data storage unit with a 32-bit word size and single bit error correction and double bit error detection (ECC) code bits. During each CPU Read cycle, a full word and its ECC bits are read from storage; and a selected 16 data bits are transferred to the CPU directly if they are error free or are corrected by the ECC logic and then transferred if they have only one bit with an error. During each CPU Write cycle, a selected full word and its ECC bits are read from storage; 16 data bits of the word are replaced by 16 data bits from the CPU; ECC bits are calculated for the modified word; and the modified word and its ECC bits are entered into the storage unit so long as no error exists in the remaining 16 bits of the data word which were not replaced/modified. This type of operation is often referred to as a Read-Modify-Write (RMW) cycle. During this RMW operation, the ECC logic detects and corrects a single bit error (if one exists) concurrent with modification of the word and calculation of new ECC bits. The corrected word is then modified by the data bits from the CPU, new ECC bits are calculated and the latter modified word and ECC bits are entered into the storage unit rather than the former word which contained a single bit error. If no error exists, a short RMW cycle is used; if a single bit error exists a longer RMW cycle is used.

REFERENCES:
patent: 3814921 (1974-06-01), Nibby
patent: 4072853 (1978-02-01), Barlow
patent: 4077565 (1978-03-01), Nibby
patent: 4249253 (1981-02-01), Gentili
patent: 4317201 (1982-02-01), Sedalis
patent: 4319356 (1982-03-01), Kocol
patent: 4646304 (1987-02-01), Fossati
Purge Your Memory Array of Pesky Error Bits, EDN Magazine--May 20, 1980, pp. 153-158.

Affiliated with

Also associated with

Rating

Error checking and correcting for read-modified-write operations does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Error checking and correcting for read-modified-write operations, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Error checking and correcting for read-modified-write operations will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-586781