Error checked high speed shift matrix

Details Error checked high speed shift matrix Error checked high speed shift matrix

1983-07-20

1985-12-03

Atkinson, Charles E.

Excavating

364738, 364900, G06F 1110

Patent

active

045569789

ABSTRACT:
A 72-bit shift matrix, suitable for LSI implementation in gate arrays, is disclosed. Eight byte shifters and eight bit shifters are combined to produce shifts of 0-72 places in either direction, circularly or open ended with zero or sign fill. A means is additionally provided to regenerate original source parity from the matrix outputs for use in thru checking. A single 9-bit parity generator is all that is required to check the correctness of the matrix.

REFERENCES:
patent: 4131940 (1978-12-01), Moyer
patent: 4348742 (1982-09-01), O'Brien
patent: 4462102 (1984-07-01), Povlick
patent: 4484259 (1984-11-01), Palmer et al.
Schaughency, Partial Parity Predict for CPU Having Architectural Rotate and Mask/Merge Unit, IBM Tech. Discl. Bulletin, vol. 23, No. 9, Feb. 1981, pp. 4126-4127.
Cash et al., N-Chip Cascadable Shift Register with Parity Predictor, IBM Tech. Discl. Bulletin, vol. 20, No. 4, Sep. 1977, pp. 1544-1547.

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