Error check code generating device and transmission error detect

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G06F 1110

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050621114

ABSTRACT:
There are disclosed an FCS encoder responsive to data to be transmitted for generating a frame check sequence (FCS) code to check a transmission error, and an FCS decoder for detecting an error. These FCS encoder and FCS decoder have a division circuit and a multiplication circuit each of which comprises shift registers in 16 stages and EXOR gates. Since there is no need for logical elements to be connected between the respective shift registers, this FCS encoder can be constituted to show a regular circuit layout on a semiconductor substrate.

REFERENCES:
patent: 4414667 (1983-11-01), Bennett
patent: 4677623 (1987-06-01), Iwasaki
patent: 4771429 (1988-09-01), Davis
Vincent Alisouskas and Wayne Tomasi "Digital and Data Communication", Prentiss-Hall Inc. (1985), pp. 50-53, 210-211.
Fasclcle, VIII.II.-Rec. vol. 41, pp. 272-273.

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