Error allowing pattern matching circuit

Details Error allowing pattern matching circuit Error allowing pattern matching circuit

1995-03-15

1998-01-20

Chung, Pnung

Excavating

371 211, 371 671, G06F 1100

Patent

active

057107750

ABSTRACT:
An error allowing pattern matching circuit comprises a data conversion circuit which converts receive data transmitted serially thereto from an input terminal into parallel data and outputs the parallel data, a ROM to which the parallel data from the data conversion circuit are inputted as an address signal and which outputs the numbers of error bits for four different particular patterns to be detected in response to the address signal, four setting circuits for setting the allowable numbers of error bits for the receive data, and four comparison circuits which individually compare the four sets of error bit numbers outputted from the ROM with the allowable numbers of error bits set by the four setting circuits, each generating the receive data when the error bit number becomes lower than the corresponding allowable number of error bits as a detection pulse.

REFERENCES:
patent: 4686690 (1987-08-01), Sato
patent: 4747116 (1988-05-01), Yajima et al.
patent: 5228036 (1993-07-01), Okamoto et al.
patent: 5473615 (1995-12-01), Boyer et al.

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