Erasing storage nodes in a bi-directional nonvolatile memory...

Details Erasing storage nodes in a bi-directional nonvolatile memory... Erasing storage nodes in a bi-directional nonvolatile memory...

2005-07-05

2005-07-05

Phung, Anh (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185240, C365S185270

Reexamination Certificate

active

06914820

ABSTRACT:
A memory transistor having a pair of separate floating gates overlying end regions of a channel and a control gate that overlies the floating gates and a central region of the channel effectively operates as a pair of floating gate transistors with an intervening select transistor. Each floating gate can be charged to store a distinct binary, analog, or multi-bit value. An erase operation can use a negative voltage on the control and a positive voltage on an underlying well or source/drain region to cause tunneling that discharges one or both floating gates. Applying a limited current to a source/drain region during an erase operation can cause the source/drain region and a floating gate to rise together and avoid band-to-band tunneling and resulting hole injection into the floating gate.

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