Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2005-12-06
2008-09-30
Dinh, Son (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185180, C365S185270
Reexamination Certificate
active
07430138
ABSTRACT:
Voltage conditions applied to the memory cells of a non-volatile memory system are changed during erase operations in order to equalize the erase behavior of the select memory cells with other memory cells of the system that are being concurrently erased. The changed conditions can compensate for capacitively coupled voltages within a NAND string. After biasing a NAND string for an erase operation and beginning application of the erase voltage pulse, the word lines of one or more interior memory cells can be floated. By floating the selected interior word lines, the peak erase potential created across the tunnel dielectric region of the cells coupled thereto is decreased from its normal level. Consequently, the erase rates of these cells are slowed to substantially match that of the slower erasing end memory cells of the string. Different word lines can be floated at different times to alter the erase behavior of different memory cells by different amounts.
REFERENCES:
patent: 4489400 (1984-12-01), Southerland, Jr.
patent: 4580247 (1986-04-01), Adam
patent: 5293337 (1994-03-01), Aritome et al.
patent: 5428568 (1995-06-01), Kobayashi et al.
patent: 5491809 (1996-02-01), Coffman et al.
patent: 5570315 (1996-10-01), Tanaka et al.
patent: 5576993 (1996-11-01), Hong
patent: 5652719 (1997-07-01), Tanaka et al.
patent: 5768188 (1998-06-01), Park et al.
patent: 5808338 (1998-09-01), Gotou
patent: 5841721 (1998-11-01), Kwon et al.
patent: 5963477 (1999-10-01), Hung
patent: 5978270 (1999-11-01), Tanaka et al.
patent: 5995417 (1999-11-01), Chen et al.
patent: 6041001 (2000-03-01), Estakhri
patent: 6130841 (2000-10-01), Tanaka et al.
patent: 6157570 (2000-12-01), Nachumovsky
patent: 6166962 (2000-12-01), Chen et al.
patent: 6198662 (2001-03-01), Chen et al.
patent: 6222773 (2001-04-01), Tanzawa et al.
patent: 6249459 (2001-06-01), Chen et al.
patent: 6353556 (2002-03-01), Chen et al.
patent: 6381174 (2002-04-01), Roohparvar et al.
patent: 6421276 (2002-07-01), Goltman
patent: 6452840 (2002-09-01), Sunkavalli et al.
patent: 6459615 (2002-10-01), McPartland et al.
patent: 6483751 (2002-11-01), Chen et al.
patent: 6519184 (2003-02-01), Tanaka et al.
patent: 6525964 (2003-02-01), Tanaka et al.
patent: 6529413 (2003-03-01), Lee et al.
patent: 6618288 (2003-09-01), Akaogi et al.
patent: 6620682 (2003-09-01), Lee et al.
patent: 6643183 (2003-11-01), Atsumi et al.
patent: 6643184 (2003-11-01), Pio
patent: 6643188 (2003-11-01), Tanaka et al.
patent: 6646920 (2003-11-01), Takashina et al.
patent: 6661711 (2003-12-01), Pan et al.
patent: 6664587 (2003-12-01), Guterman et al.
patent: 6704222 (2004-03-01), Guterman et al.
patent: 6711066 (2004-03-01), Tanzawa et al.
patent: 6744670 (2004-06-01), Tamada et al.
patent: 6771541 (2004-08-01), Park
patent: 6842380 (2005-01-01), Lakhani et al.
patent: 6859397 (2005-02-01), Lutze et al.
patent: 6862223 (2005-03-01), Lee et al.
patent: 6894931 (2005-05-01), Yaegashi et al.
patent: 7009889 (2006-03-01), Tran et al.
patent: 7057936 (2006-06-01), Yaegashi et al.
patent: 7079437 (2006-07-01), Hazama et al.
patent: 7102929 (2006-09-01), Lee et al.
patent: 2002/0133679 (2002-09-01), Choi et al.
patent: 2003/0123296 (2003-07-01), Hirano
patent: 2003/0147278 (2003-08-01), Tanaka wt al.
patent: 2003/0189864 (2003-10-01), Sim
patent: 2004/0141378 (2004-07-01), Tanzawa et al.
patent: 2005/0041515 (2005-02-01), Futatsuyama et al.
patent: 2005/0105373 (2005-05-01), Takase et al.
patent: 2005/0128805 (2005-06-01), Lee et al.
patent: 2006/0140012 (2006-06-01), Wan et al.
patent: 2006/0221660 (2006-10-01), Hemink et al.
patent: 2006/0221661 (2006-10-01), Hemink et al.
patent: 2006/0221703 (2006-10-01), Higashitani
patent: 2006/0221705 (2006-10-01), Hemink et al.
patent: 2006/0221709 (2006-10-01), Hemink et al.
patent: 2006/0279992 (2006-12-01), Park et al.
patent: 2006/0285387 (2006-12-01), Micheloni et al.
patent: 0024002 (2000-04-01), None
patent: 2004013864 (2004-02-01), None
Non-final Office Action, United States Patent & Trademark Office, U.S. Appl. No. 11/296,055, filed Dec. 6, 2005, Oct. 2, 2007.
Notice of Allowance and Fee(s) Due, United States Patent & Trademark Office, U.S. Appl. No. 11/296,032, filed Dec. 6, 2005, Nov. 21, 2007.
Response to Non-Final Office Action, U.S. Appl. No. 11/296,032, filed Dec. 6, 2005, Jul. 27, 2007.
Notice of Allowance and Fee(s) Due, United States Patent & Trademark Office, U.S. Appl. No. 11/025,620 entitled, “Word Line Compensation in Non-Volatile Memory Erase Operations,” Mar. 20, 2007.
Office Action, Non-Final, United States Patent & Trademark Office, U. S. Appl. No. 11/296,032 entitled, “Systems for Erasing Non-Volatile Memory Utilizing Changing Word Line Conditions to Compensate for Slower Erasing Memory Cells,” Feb. 28, 2007.
Office Action, Non-Final, United States Patent & Trademark Office, U.S. Appl. No. 11/296,028 entitled,“Systems for Erasing Non-Volatile Memory Using Individual Verification and Additional Erasing of Subsets of Memory Cells,” Mar. 12, 2007.
Office Action, Election/Restriction, United States Patent & Trademark Office, U.S. Appl. No. 11/296,032 entitled, “Systems for Erasing Non-Volatile Memory Utilizing Changing Word Line Conditions to Compensate for Slower Erasing Memory Cells,” Nov. 8, 2006.
Office Action, Election/Restriction, United States Patent & Trademark Office, U.S. Appl. No. 11/296,028 entitled, “Systems for Erasing Non-Volatile Memory Using Individual Verification and Additional Erasing of Subsets of Memory Cells,” Dec. 6, 2006.
Notice of Allowance and Fee(s) Due, United States Patent & Trademark Office, U.S. Appl. No. 11/296,071 entitled, “Systems for Soft Programming Non-Volatile Memory Utilizing Individual Verification and Additional Soft Programming of Subsets of Memory Cells,” Dec. 5, 2006.
Notice of Allowance and Fee(s) Due, United States Patent & Trademark Office, U.S. Appl. No. 11/296,071 entitled, “Systems for Soft Programming Non-Volatile Memory Utilizing Individual Verification and Additional Soft Programming of Subsets of Memory Cells,” Apr. 9, 2007.
Office Action, Non-Final, United States Patent & Trademark Office, U.S. Appl. No. 11/025,620 entitled, “Word Line Compensation in Non-Volatile Memory Erase Operations,” Mar. 31, 2006.
Supplemental Notice of Allowability, United States Patent & Trademark Office, U.S. Appl. No. 11/025,620 entitled, “Word Line Compensation in Non-Volatile Memory Erase Operations,” Mar. 26, 2007.
Non-Final Office Action, United States Patent & Trademark Office, U.S. Appl. No. 11/025,620, filed Dec. 29, 2004, Jul. 13, 2007.
International Preliminary Report on Patentability (Chapter 1 of the Patent Cooperation Treaty), Patent Cooperation Treaty, Application No. PCT/US2005/045557 filed on Dec. 15, 2005, Jul. 12, 2007.
Tetsuo Endoh, et al., “A Study of High-Performance NAND Structured EEPROMS,” IEICE Transactions on Electronics, Electronics Society, Tokyo, Japan, vol. E75-C, No. 11, Nov. 1, 1992, pp. 1351-1356.
Dinh Son
SanDisk Corporation
Vierra Magen Marcus & DeNiro LLP
LandOfFree
Erasing non-volatile memory utilizing changing word line... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Erasing non-volatile memory utilizing changing word line..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Erasing non-volatile memory utilizing changing word line... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3965210