Erasing method for p-channel NROM

Details Erasing method for p-channel NROM Erasing method for p-channel NROM

2001-10-22

2003-12-30

Ho, Hoai (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185180, C365S185260, C365S185270

Reexamination Certificate

active

06671209

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 90124032, filed Sep. 28, 2001.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates in general to an erasing method for a p-channel Silicon Nitride Read Only Memory, (p-channel NROM), and more specifically relates to an erasing method for a p-channel NROM by means of band-to-band induced hot electron injection.
2. Description of Related Art
Electrically erasable programmable read only memories (EEPROMs) are programmable and erasable, and the data stored in the EEPROMs can be kept even though the EEPROMs are powered off. Therefore, the EEPROMs are widely used in personal computers and electrical devices.
Among the electrically erasable programmable read only memories (EEPROMs), the EEPROM with an oxide-nitride-oxide (ONO) structure is massively studied because a nitride layer of the ONO structure can be used to trap and store electrons. For programming or erasing EEPROM with the ONO structure, the nitride layer in the ONO structure serves as a charge-trapping layer for replacing a conventional floating gate of a flash memory cell. At present, several EEPROMs with the ONO structure are developed, for example a silicon-oxide-nitride-oxide-silicon (SONOS) ROM and a nitride ROM (NROM). The SONOS ROM advantages low operational voltages and therefore the cell size can be reduced for further increasing the integration. Electrons injected into the nitride layer of the NROM cell are localized and therefore sensitivity for defects of the tunneling oxide layer is smaller, resulting in low leakage current. Furthermore, two bits can be programmed into a single cell (1 cell 2 bit), meaning that four storage states can be made within a single NROM cell. Therefore, the EEPROM with the ONO structure provides a better device efficiency.
On the other hand, the p-channel memory device is superior to the n-channel memory device because of high electron injection efficiency, high scalability, reliability preventing holes form injection, and a lower electric field for the tunneling oxide during electron injection. Therefore, a p-channel EEPROM with the ONO structure has advantages and perspective for development in the future.
However, for a p-channel SONOS ROM, the Fowler-Nordheim (F-N) tunneling effect is used for programming the memory cell. All electrons in the channel tunnel through the barrier of a tunneling oxide layer (the oxide layer of the ONO structure) into the nitride layer, and distribute uniformly in the nitride layer. As a result, one SONOS ROM cell can only store one bit.
In addition, it also utilizes the Fowler-Nordheim (F-N) tunneling effect to erase the memory cell. Then, all electrons stored in the nitride layer tunnel through the barrier of the tunneling oxide layer into the substrate. However, the SONOS memory device can only be erased by block, rather than by cell, causing many restrictions on the operation of program, erase and read for the SONOS memory device.
Conventionally, channel hot electron injection is used for erasing the p-channel NROM. Electrons are injected from the nitride layer to the drain through the tunneling oxide. One of the drawbacks is that the channel has to be opened when the p-channel NROM is erased by the channel hot electron injection, causing that the leakage current is easily occurred. Another drawback is that the two-bit data stored in the p-channel NROM are erased simultaneously, and therefore erasing operation is restricted because of the foregoing reasons.
SUMMARY OF THE INVENTION
According to the foregoing drawbacks of the erasing operation for the p-channel SONOS ROM or p-channel NROM, an object of the invention is to provide an erasing method for a p-channel NROM without opening its channel, thereby the drain leakage current is not occurred and the power consumption is reduced.
It is another object to provide an erasing method for a p-channel NROM capable of erasing by single bit or two bits for a single cell, or capable of erasing by byte, sector or block for a memory array.
The invention provides an erasing method for a p-channel nitride read only memory. The method is used for a p-channel nitride read only memory having charges stored in a charge-trapping layer. A positive voltage is applied to the control gate and a negative voltage to the drain; also, the source is floating and the n-well is grounded. The voltage difference between the positive voltage applied to the control gate and the negative voltage to the drain is sufficient to trigger a band-to-band induced hot electron injection to erase the p-channel nitride read only memory.


REFERENCES:
patent: 6172397 (2001-01-01), Oonakado et al.
patent: 6331952 (2001-12-01), Wang et al.
patent: 6441443 (2002-08-01), Hsu et al.

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