Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-07-05
2002-08-27
Zarabian, Amir (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185190
Reexamination Certificate
active
06442075
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an erasing method for a nonvolatile semiconductor memory device, and more particularly, to an erasing method for a nonvolatile semiconductor memory device which makes it possible to improve a threshold voltage distribution after executed an erasing operation in the nonvolatile semiconductor memory device employing a writing method with use of channel hot electrons.
As a most commonly used flash memory, there has conventionally been an ETOX (EPROM THIN OXIDE: Trademark of Intel Co.). A schematic cross sectional view of this ETOX-type flash memory cell is shown in FIG.
9
. As shown in
FIG. 9
, on a source
1
, a drain
2
, and a substrate (well)
3
between the source and the drain, there is formed a floating gate
5
with a tunnel oxide
4
interposed. Further on the floating gate
5
, there is formed a control gate
7
with an interlayer insulating film
6
interposed.
Description will be now given of an operational principle of the ETOX-type flash memory. In a writing operation, as shown in Table 1, a voltage Vpp (ex., 10V) is applied to the control gate
7
, a reference voltage Vss (ex.,
0
V) is applied to the source
1
, and a voltage of 6V is applied to the drain
2
. Consequently, a large current flows through a channel layer, and hot electrons are generated in an area with high electric fields on the drain
2
side, by which electrons are injected into the floating gate
5
. As a result, a threshold voltage is increased and writing onto a certain memory cell is executed.
FIG. 10
shows a threshold voltage distribution in a written state and in an erased state. As shown in
FIG. 10
, threshold voltages of memory cells in the write state are 5V or more.
TABLE 1
Control
gate 7
Drain 2
Source 1
Substrate 3
Writing
10
V
6 V/0 V
0 V
0 V
Erasing
−9
V
Open
4 V
0 V
Reading
5
V
1 V
0 V
0 V
In an erasing operation, as shown in
FIG. 11
, a voltage Vnn (ex., −9V) is applied to the control gate
7
, a voltage Vpe (ex., 4V) is applied to the source
1
, and the drain
2
is set to be open, so that electrons are pulled toward the source
1
side and the threshold voltage is decreased. As a result, as shown in
FIG. 10
, the threshold voltages of memory cells in an erased state are 0.5V to 3V. In this case, a BTBT (Band To Band Tunneling) current flows from the source
1
to the Substrate (well)
3
. Upon generation of this current, hot holes and hot electrons are also generated. The hot electrons flow away to the drain
2
, whereas the hot holes are pulled toward the tunnel oxide
4
side and trapped inside the tunnel oxide
4
. Generally, this phenomenon is considered to be a cause of deteriorated reliability.
In a reading operation, a voltage of 1V is applied to the drain
2
, and a voltage of 5V is applied to the control gate
7
. Herein, if a memory cell is in an erased state and low in the threshold voltage, current flows into the memory cell and status of the memory cell is determined to be “1”. If the memory cell is in a written state and high in the threshold voltage, current does not flow into the memory cell, and status of the memory cell is determined to be “0”.
As described above, the operation with use of applied voltages shown in Table 1 has a problem that a BTBT current generated in the erasing operation causes deteriorated reliability of the memory cells. As one solution of this problem, there is a method of conducting, at the time of erasing, a channel erasing operation which does not generate the BTBT current. Herein, the erasing operation that pulls electrons toward the source
1
side as described above is called a “source-side erasing operation”. It is noted that a writing operation and a reading operation in the case of conducting the channel erasing operation are identical to the case of conducting the source-side erasing operation.
Hereinbelow, description will be made of the channel erasing operation. Table 2 shows voltage application conditions in each writing, erasing, and reading access to ETOX-type flash memory cells in the case of conducting the channel erasing operation.
TABLE 2
Control
gate 7
Drain 2
Source 1
p Well 8
Writing
10
V
6 V/0 V
0 V
0 V
Erasing
−9
V
Open
7 V
7 V
Reading
5
V
1 V
0 V
0 V
In the above channel erasing, as shown in
FIG. 12
, a voltage Vnn (ex., −9V) is applied to the control gate
7
, and a voltage Vesc (ex., +7V) is applied to the source
1
and a first well (p well)
8
. Consequently, strong electric fields are applied to the tunnel oxide
4
disposed between a channel layer and the floating gate
5
, and due to an FN (Fowler-Nordheim) tunneling phenomenon, electrons are pulled from the floating gate
5
toward the channel side, resulting in decrease of the threshold voltage. As shown in
FIG. 10
, a threshold voltage distribution in a written and an erased state is approximately identical to that in the source-side erasing operation.
In this case, potential of the source
1
is equal to potential of the first well (p well: channel region)
8
, so that electric fields are not concentrated onto an interface between the source
1
and the well
8
, and therefore the BTBT current is not generated. As a result, hot hole trap is not generated, resulting in improved reliability of the memory cells.
However, the above-described channel erasing operation has a problem that dispersion in the threshold voltage distribution after an erasing operation, attributed to dispersion of a channel length, is larger than that in the source-side erasing operation, as indicated in “Comparison of Current Flash EEPROM Erasing Methods: Stability and How to control” IEDM Tech. Dig 1992 IEDM 92-595 (reference 1). Therefore, the channel erasing operation requires control of dispersion in the threshold voltage after executed the erasing operation.
As one solution to this problem, there is a method disclosed in “Control of Erased Flash Memory's Threshold Voltage by 2-Step Erasing Scheme”, Technical Report SDM93-29 1993 of Institute of Telecommunications Engineers (reference 2). Applying this method to a memory cell structure of
FIG. 12
results in applied voltage waveforms shown in FIG.
13
. As shown in
FIG. 13
, the two-step erasing method is made up of a first step and a second step. In the first step, a voltage Vnn (ex., −9V) is applied to the control gate
7
, and a voltage Vesc (ex., +7V) is applied to the source
1
and the first well (channel region)
8
. In the second step, a voltage Vpcg (ex., 10V) is applied to the control gate
7
, and a voltage Vpsc (ex., −7V) is applied to the source
1
and the first well (channel region)
8
. An operation in the first step is identical to the normal channel erasing operation shown in
FIG. 12
, where the threshold voltage is decreased by the erasing operation. On the other hand, an operation in the second step is, as shown in
FIG. 14
, to inject electrons from a channel layer
10
into the floating gate
5
for increasing the threshold voltage. More particularly, some writing is executed to decrease dispersion in the threshold voltage of the memory cells. Hereinafter, a writing operation shown in
FIG. 14
is referred to as a “channel writing operation”.
FIG. 15
shows a change in the threshold voltage distribution in the tow-step erasing operation. Comparison between the change in the threshold voltage distribution in FIG.
15
and that in the normal channel erasing operation of
FIG. 10
clarifies that the width of the threshold voltage distribution in the erased state is narrow and tight with the two-step erasing method. This indicates that the two-step erasing method is effective for achieving a tight threshold voltage distribution after executed the erasing operation.
The following description discusses a mechanism of the phenomenon shown in
FIG. 15
with reference to
FIGS. 16 and 17
, and a model equation of the FN tunnel current (for detail, see the reference 2). The FN tunnel current J
FN
is expressed by an equation (1):
J
FN
=
A
E
2
exp
&emsp
Morrison & Foerster / LLP
Sharp Kabushiki Kaisha
Zarabian Amir
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