Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2007-07-03
2007-07-03
Mai, Son L. (Department: 2827)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185140, C365S185170, C365S185290
Reexamination Certificate
active
11308018
ABSTRACT:
An erasing method for a non-volatile memory is provided. The method includes the following two major steps. (a) A first voltage is applied to the odd-numbered select gates of each memory row and a second voltage is applied to the even-numbered select gates of each memory row such that the voltage difference between the first voltage and the second voltage is large enough for the electrons injected into the floating gate of the memory cells to be removed via the select gate. (b) A switchover operation is performed so that the first voltage is applied to the even-numbered select gates of each memory row and the second voltage is applied to the odd-numbered select gates of each memory row such that the electrons injected into the floating gates of the memory cells are pulled away via the select gates to turn the memory cells into an erased state.
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Chu Kuo-Hao
Hsu Cheng-Yuan
Pan Yen-Lee
Wang Kuo-Tung
Jiang Chyun IP Office
Mai Son L.
Powerchip Semiconductor Corp.
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