Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2005-04-19
2005-04-19
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185300, C365S218000, C365S185330
Reexamination Certificate
active
06882575
ABSTRACT:
An erasing method for the memory cells of a non-volatile memory is provided. Each memory cell comprises a gate, a source, a drain, an electron-trapping layer and a substrate. The data within the memory cell is erased by applying a first voltage to the control gate, applying a second voltage to the source, applying a third voltage to the drain and applying a fourth voltage to the substrate. The electrons are pulled from the electron-trapping layer into the channel by negative gate F-N tunneling effect.
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Lu Tao-Cheng
Pan Samuel C.
Tsai Wen-Jer
Yeh Chih-Chieh
J.C. Patents
Macronix International Co. Ltd.
Nguyen Viet Q.
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