Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-11-06
2004-12-07
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185300, C365S218000, C365S185330
Reexamination Certificate
active
06829175
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial No. 91120417, filed Sep. 9, 2002.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of operating non-volatile memory. More particularly, the present invention relates to an erasing method for non-volatile memory.
2. Description of Related Art
Non-volatile memory such as the electrically erasable programmable read only memory (EEPROM) is a device for holding data. Data stored inside the memory can be read or erased a multiple of times, and furthermore, the data is retained even after power is turned off. Hence, EEPROM has become one of the principal devices inside a personal computer or electrical equipment.
The floating gate and the control gate of a typical EEPROM are fabricated using doped polysilicon. To program the memory, electrons injected into the floating gate will distribute evenly over the entire polysilicon floating gate layer. However, if the tunnel layer underneath the polysilicon floating gate layer contains defects, leakage current may flow and compromise the reliability of the device.
To prevent leakage current flowing inside an EEPROM, an electron-trapping layer is often used instead of a polysilicon floating gate layer. The electron-trapping layer is a layer of silicon nitride, for example. In general, a layer of silicon oxide is also formed both above and below the electron-trapping layer to form an oxide
itride/oxide (ONO) composite stacked gate structure. An EEPROM having a stacked gate structure is often referred to as a nitride read-only-memory (nitride ROM). When voltages are applied to the control gate and the source/drain terminals of the device in a programming operation, hot electrons generated in the channel region close to the drain will inject into the electron-trapping layer. Since silicon nitride has the special property of capturing electrons, the injected electrons will concentrate within certain local areas of the electron-trapping layer instead of distributing evenly over the entire electron-trapping layer. Due to the localization of the electrons within the electron-trapping layer, sensitivity to defects in the tunnel oxide layer is reduced and hence leakage current is greatly minimized.
Another advantage of a nitride ROM is that the source/drain terminal on one side of the stacked gate may receive a higher voltage during a programming operation so that electrons are trapped inside the silicon nitride layer close to the source/drain terminal. Alternatively, the source/drain terminal on the other side of the stacked gate may receive a higher voltage so that electrons are trapped inside the silicon nitride layer close to that side of the source/drain terminal. Thus, by varying the voltage applied to the source/drain terminal on each side of the control gate, a single silicon nitride layer may be able to host two batches of electrons, a single batch of electrons or no electrons at all. In other words, a total of four states may be written into each memory cell of a nitride ROM. That means the nitride ROM is a two bits per cell type of non-volatile memory.
A conventional nitride ROM is programmed using channel hot electrons. Hot electrons injected from the drain side (or the source side) will penetrate through the tunnel oxide layer into the electron-trapping layer and are stored locally close to the area above the drain (or the source). Since the electron-trapping layer on the drain side (or the source side) has an excess of negative charges after the programming operation, threshold voltage (V
T
) of the memory cell will increase. These trapped electrons will remain inside the electron-trapping layer for a very long time (for example, up to 10 years at a temperature of 85° C.) unless they are purposely erased in an erasing operation. To erase the electrons from the electron-trapping layer, holes on the drain side (source side) may penetrate the tunnel oxide layer into the electron-trapping layer in a band-to-band tunneling induced hot hole injection. Since the original negative electric charges inside the drain side (or source side) electron-trapping layer are neutralized by the holes after an erasing operation, threshold voltage (V
T
) of the memory cell will drop to re-constitute the erase state.
However, the quantity of holes injected from the drain side (or source side) into the electron-trapping layer is difficult to control if the band-to-band tunneling induced hot hole injection is utilized. Because of this, an excess of holes may be injected into the electron-trapping layer during erase and produce a so-called over-erase state in the memory device. When the degree of over-erasure is severe, reliability of the memory device may be compromised. The situation is particularly serious for a memory device having a small overall dimension. Thus, using band-to-band tunneling induced hot hole injection to carry out data erasure will ultimately limit the degree of miniaturization of memory devices.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide an erasing method for non-volatile memory capable of preventing over-erasure, improving reliability and lowering operating current.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides an erasing method for non-volatile memory. The non-volatile memory comprises a gate, a source, a drain, an electron-trapping layer and a substrate. The method includes applying a first voltage to the gate, a second voltage to the source, a third voltage to the drain and a fourth voltage to the substrate so that electrons are pulled out from the electron-trapping layer into the channel in the erasing operation. The difference between the first voltage applied to the control gate and the fourth voltage applied to the substrate is high enough to produce a negative gate F-N tunneling effect for erasing data within the non-volatile memory. Furthermore, the second voltage applied to the source, the third voltage applied to the drain and the fourth voltage applied to the substrate have identical value so that few holes are produced inside the substrate. Consequently, stress caused by the presence of holes is minimized.
The aforementioned erasing method is equally applicable to a non-volatile memory having two bits per cell storage capacity or a non-volatile memory having one bit per cell storage capacity.
This invention also provides a method of operating a non-volatile memory. The non-volatile memory includes a gate, a source, a drain, an electron-trapping layer and a substrate. The method includes programming the non-volatile memory to a programming threshold voltage Vt
P
. Thereafter, the non-volatile memory is set to an erased threshold voltage Vt
E
through a negative gate F-N tunneling effect by applying a first voltage to the gate, a second voltage to the source, a third voltage to the drain and a fourth voltage to the substrate. The difference between first voltage applied to the gate and the fourth voltage applied to the substrate is high enough to produce a negative gate F-N tunneling effect for erasing data within the non-volatile memory. Furthermore, the second voltage applied to the source, the third voltage applied to the drain and the fourth voltage applied to the substrate have identical value so that few electric holes are produced inside the substrate and stress caused by the holes is restrained.
The aforementioned operating method is equally applicable to a non-volatile memory having two bits per cell storage capacity or a non-volatile memory having one bit per cell storage capacity.
Since the negative gate F-N tunneling effect raises the threshold voltage from the initial threshold voltage Vti (the initial state) to the erase threshold voltage Vt
E
(the erase state), charges within the electron-trapping layer are already evenly distributed when the memory cells are in the erase state. This prevents residual holes
Lu Tao-Cheng
Pan Samuel C.
Tsai Wen-Jer
Yeh Chih-Chieh
J.C. Patents
Macronix International Co. Ltd.
Nguyen Viet Q.
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