Erasing device and method of erasure for a storage unit, and sto

Details Erasing device and method of erasure for a storage unit, and sto Erasing device and method of erasure for a storage unit, and sto

1999-05-28

2000-09-12

Tran, Andrew

Static information storage and retrieval

Floating gate

Particular biasing

36518529, G11C 1604

Patent

active

061187046

ABSTRACT:
In an erasing device or method for a storage unit, or a storage medium storing a program for erasing the storage unit, an output VS of a column decoder and a reference voltage VR are compared at a sense amplifier, while an erase operation is executed by taking out an electric charge of each cell in a memory cell array, after which the output of the sense amplifier is evaluated at a data determination circuit, and a signal DD is counted by a bit counter under the condition of VS<VR. As the entirety of addresses of an address signal ADD from an internal address increment circuit are finished, a signal FG rises. When a count number of a bit counter is above a predetermined number, an erasing routine is terminated, and thus it is possible to prevent the majority of the bits from falling into a state of depression.

REFERENCES:
patent: 5327383 (1994-07-01), Merchant et al.
patent: 5475249 (1995-12-01), Watsuji et al.
patent: 5600593 (1997-02-01), Fong
patent: 5625600 (1997-04-01), Hong
patent: 5781477 (1998-07-01), Rinerson et al.
patent: 5831905 (1998-11-01), Hirano

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