Erasing circuit for a flash memory device having a triple well s

Details Erasing circuit for a flash memory device having a triple well s Erasing circuit for a flash memory device having a triple well s

1998-08-28

2000-04-18

Nelms, David

Static information storage and retrieval

Floating gate

Particular biasing

36518518, 36518519, 36518527, 36518529, 36518523, G11C 1604

Patent

active

060523050

ABSTRACT:
The present invention discloses a flash memory device, a first well and second well are formed in a substrate, a plurality of memory cell are formed in the second well and arranged in an array having a multiplicity of bit lines and word lines. Voltage is applied to the first well and second well, respectively, with time interval so that an over erasing of the memory cell and lowering of cycling characteristic can be prevented.

REFERENCES:
patent: 4667312 (1987-05-01), Doung et al.
patent: 5457652 (1995-10-01), Brahmbhatt
patent: 5862078 (1999-01-01), Yeh et al.
patent: 5872733 (1999-02-01), Buti et al.
patent: 5894438 (1999-04-01), Yang et al.

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