Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2000-06-13
2001-11-06
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S230060, C365S189040, C365S185290
Reexamination Certificate
active
06314043
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention concerns a circuit for parallel erasing and rewriting of blocks of memory cells and particularly for analog flash cells, and related operating method.
2. Discussion of the Related Art
The bits in a memory matrix can be addressed both individually and in blocks. If, for instance, a bit in a memory of 4M bits is addressed, 22 bits of address will be necessary, being 2
22
=4194304. Otherwise, if one addresses by byte, that is 8 bits at a time, it will be necessary to have 19 as address.
The memory matrix is made up of floating gate cells in which the bits are stored. By injecting a certain charge in the floating gate, during the programming operation, it is possible to increase the value of the threshold voltage of the cell in a permanent way. The threshold voltage of the cell corresponds to a certain logic level, and in this way by rereading the value of said voltage with suitable circuits, called “sense amplifiers”, it is possible to determine which bit or bits are stored in the cell.
In fact, each memory cell is capable of storing one or more bits, according to whether the threshold has been programmed on two or more levels, respectively. For instance 16 levels correspond to 4 bits for each cell.
Finally the cells can be erased electrically by extracting the charges trapped in the floating gate.
The writing of a datum in a cell presupposes that said cell is virgin or erased, that is it has a low threshold level.
In some applications the minimum unit of transfer is 512 bytes. In these cases, if even one cell of a block to be programmed has been previously programmed, it is necessary to apply the erasing algorithm to the entire block and subsequently to carry out the programming operation. The specifications on writing times also include the time necessary to carry out the erasing operation, thus imposing very strict limitations both on the programming times and on the erasing times.
The programming, or writing, operation involves one or more cells belonging to the same row and said operation can be executed by applying positive voltage pulses, for instance pulses having a step shaped wave, on the row, that is on the gate electrodes of each cell, and a voltage, either continuous or pulsed, on the drain electrode of each cell to be programmed, while putting the source electrode of each cell at ground and the bulk electrode of each cell at ground or at a negative voltage.
The situation that is thus created, during the programming operation, is therefore the following: the gate electrodes of the row to be programmed have a positive voltage, for instance +5V, while all the other rows are at ground, the source electrodes are at ground, the bulk electrodes are at ground or have a negative voltage, for instance −5V, the drain electrodes of the column to be programmed are +5V while the other columns are floating.
The flash memory, because of the way it is conceived, does not allow the erasing of the single cell, since in order to increase the cell density and therefore to increase the density of recordable data, it is made in a such way that the source and bulk terminals of the single cells are common. With the current state of the art, the matrix of the flash memory is divided into sectors, each one erasable independently from the others.
The erasing operation in the flash memories consists in extracting all the charges trapped in the floating gate of each cell by application of one or more erasing pulses.
After the erasing operation, in order to allow a correct data storing operation, particularly if the memory is of multilevel type, it is necessary, in first place, not to let any cell go into depletion (too low threshold) and, in second place, that at the end of the process all cells have a threshold voltage lower than a certain value. In addition, at the end of the process all the thresholds of the cells to be erased must be within a well established and not too wide interval of values.
In a previous Italian patent application No. MI99A00859 filed on Apr. 23, 1999 a method that allows relaxation of the conditions to perform the erasing operation was described. In said method the cells of the memory sector taken into consideration must meet less strict conditions in terms of writing and erasing times, since the new data to be written in the same sector are used as references for each cell. These techniques allow decreasing the average time of the erasing operation.
The erasing operation of a row of a sector of the memory matrix, according to such method, is done by setting a negative voltage on the gate line of the row that must be erased, a positive voltage on the bulk and/or source electrodes of the sector and a positive voltage on the gates of the other rows of the sector, while leaving the drain electrodes, which represent the columns of the memory sector, floating.
The situation that is thus created during the erasing operation is therefore the following: the gate electrodes of the row to be erased are negative, for instance −8V, while those of the remaining rows of the block are positive, for instance +8V, the drain electrodes are floating, the bulk electrodes have a positive voltage, for instance +8V and the source electrodes have a voltage of +8V or they are floating.
In the traditional methods, in which the erasing operation involves more rows simultaneously, it can occur that during said operation one or more cells undergo depletion. This must be prevented since it would cause a reading error for all cells of that column. Besides, the cell undergoing depletion, according to the traditional method, would not be detectable among the other ones of the same column, and therefore it could not be retrieved by means of proper programming pulses.
In the method according to the application previously referred to a possible depleted cell is instead always detectable and therefore retrievable during the writing or programming operation.
This implies that instead of applying programming pulses alternated to erasing ones, in order to prevent overerasing, that is to prevent that a cell undergoes depletion, only the erasing pulse for a pre-established time is applied. This allows, in addition to an increase in the speed of the programming and writing operations, a simpler control of the memory.
The erasing operation concerns, therefore, a single row that includes a certain number of columns. This means that only a certain number of the addressing bits is necessary in order to specify which block must be erased, while the other bits, that is the ones that select the column, are as a result uninfluential.
It must be finally noticed that, when a programming operation of a memory is carried out, it often happens that several blocks must be programmed, whose minimum unit is of 512 B (byte).
In view of the state of the art above described an object of the present invention is to provide for a circuit and a method for parallel erasing and rewriting of blocks of analog flash cells and related operating method.
SUMMARY OF THE INVENTION
According to the present invention, this and other objects are achieved by means of a circuit for erasing and rewriting blocks of memory cells and particularly of analog flash cells, comprising at least one row decoding circuit, comprising at least two adder blocks, that are suitable to generate a row address signal, at least two decoder blocks, that are suitable to generate respective pluralities of signals identifying a respective sector of memory to be enabled, at least two shifter blocks, that are suitable to generate an address signal of another row to be enabled, at least two OR logic blocks, that are suitable to generate respective signals serving the purpose to enable simultaneously at least two rows of the memory matrix.
Owing to the present invention a circuit for parallel erasing and rewriting blocks of analog flash cells is provided through which the row and column decoding signals are controlled in such a way that it is possible to ca
Guaitini Giovanni
Pasotti Marco
Rolandi Pier Luigi
Galanthay Theodore E.
Morris James H.
Nelms David
STMicroelectronics S.r.l.
Wolf Greenfield & Sacks P.C.
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