Erase voltage reduction in a non-volatile memory device

Details Erase voltage reduction in a non-volatile memory device Erase voltage reduction in a non-volatile memory device

2008-11-14

2011-11-22

Nguyen, Tuan T. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185180, C365S185220, C365S185170

Reexamination Certificate

active

08064267

ABSTRACT:
In erasing a memory block of memory cells, a semiconductor tub that contains a memory block to be erased can be biased with a high, positive voltage. The control gates of the memory cells that make up the memory block can be biased with a negative voltage. An erase verification can then be performed to determine if the memory block has been successfully erased. If the memory block has not been erased, the erase operation of biasing the tub with the positive voltage and the control gates with the negative voltage can be repeated until the erase verification is successful.

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