Erase verifying apparatus in serial flash memory having redundan

Details Erase verifying apparatus in serial flash memory having redundan Erase verifying apparatus in serial flash memory having redundan

1999-02-17

2000-03-14

Nguyen, Tan T.

Static information storage and retrieval

Floating gate

Particular biasing

36518522, G11C 2900

Patent

active

060381752

ABSTRACT:
An erase verifying apparatus includes: a memory cell array including a plurality of main areas and redundant areas having one or more cells, the main areas and redundant areas forming an erase block, a wordline circuit for controlling wordlines in the memory cell array, a redundancy control unit for storing redundancy information, a data buffer for loading replacement information from the redundancy control unit, a column selector for selecting a column in the memory cell array, a sense amplifier for sensing an output from the selected cell, and a controller for controlling all operations, and an erase verifying method includes the steps of: initializing the data buffer, loading the redundancy information stored in the redundancy control unit to the data buffer, selecting a certain erase block and erasing the cell data of the selected erase block by using the wordline circuit, selecting the cells of the selected erase block sequentially, checking whether the cell of the data buffer corresponding to the selected cell is replaced by the redundancy, and checking the output from the sense amplifier when the cell of the data buffer is not replaced by the redundancy.

REFERENCES:
patent: 4701887 (1987-10-01), Ogawa
patent: 5347484 (1994-09-01), Kwong et al.
patent: 5438546 (1995-08-01), Ishac et al.
patent: 5617359 (1997-04-01), Ninomiya
patent: 5621687 (1997-04-01), Doller
patent: 5784316 (1998-07-01), Hirata

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