Erase verify scheme for NAND flash

Details Erase verify scheme for NAND flash Erase verify scheme for NAND flash

1998-06-03

1999-12-28

Nguyen, Viet Q.

Static information storage and retrieval

Floating gate

Particular biasing

36518529, 365218, 36518526, 36518533, G11C 1606

Patent

active

060090146

ABSTRACT:
The present invention provides a method of verifying that all flash EEPROM transistors in a NAND string are properly erased without overerasing by applying a bias voltage to the source of the bottom select gate of the NAND array and applying a non-negative erase verify voltage to the control gates of each transistor during an erase verify. The bias voltage is at least equal to the erased threshold voltage of the worst case transistor to ensure proper erase verification. If all transistors are not erased, then another erase operation is performed. Erasing is repeated until the erase verify operation indicates that all transistors are properly erased. By erasing and verifying according to the present invention, the NAND array is completely and properly erased while minimizing overerasing the array.

REFERENCES:
patent: 5473563 (1995-12-01), Suh et al.
patent: 5671178 (1997-09-01), Park et al.
patent: 5696717 (1997-12-01), Koh
patent: 5726934 (1998-03-01), Tran et al.
patent: 5748538 (1998-05-01), Lee et al.
patent: 5862074 (1999-01-01), Park

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