Erase scheme for non-volatile memory

Details Erase scheme for non-volatile memory Erase scheme for non-volatile memory

2002-04-02

2003-09-02

Elms, Richard (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185180, C365S185300, C365S185260, C365S185240

Reexamination Certificate

active

06614694

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor memory devices and more particularly to an erase scheme for a programmable read only memory (PROM) cell having charge trapping dielectric material in the gate.
2. Description of the Related Art
Memory devices for non-volatile storage of information are currently in widespread use today, being used in a myriad of applications.
U.S. Pat. No. 5,768,192, issued to Eitan et al., teaches an apparatus and method of programming and reading a programmable read only memory (PROM) having a trapping dielectric layer sandwiched between two silicon dioxide layers, as shown in FIG.
1
.
FIG. 1
illustrates a sectional view of a PROM cell constructed in accordance with Eitan's reference utilizing ONO as the gate dielectric. The PROM can be programmed to let electrons trapped in both sides of the silicon nitride layer
20
near the source
14
and the drain
16
(i.e. 2 bits/cell operation).
The operation of erasing data restored in the device is described. A conventional erase method is band-to-band hot-hole erase. If the silicon dioxide layer
18
is thick, for example, 20 nm or thicker, an FN tunneling current has difficulty flowing unless the voltage between the gate
24
and n-type region
14
or
16
becomes high. Therefore, the potential difference between the n-type region
14
or
16
and channel region becomes large earlier than between the n-type region
14
or
16
and gate electrode
24
and an avalanche breakdown occurs at the end portion of the n-type region
14
or
16
.
Hot holes generated by the electrons band-to band tunneling are accelerated by the electric field in the depletion layer. When the hot holes obtain a sufficiently high energy, they are injected toward the gate
24
maintained at the low potential and trapped in the silicon nitride layer
20
. Since electrons are trapped beforehand in the silicon nitride layer
20
, electrons and holes are recombined to erase the stored data.
However, band-to-band hot-hole erase will result in serious read disturb which may come from the residual hole traps in silicon dioxide layer
18
assisting electron tunneling and channel shortening enhancing lateral field. Serious read disturb may also cause window closure and can be an issue for device scaling.
SUMMARY OF THE INVENTION
The object of the present invention is to perform a soft anneal after band-to-band hot-hole erase. The soft anneal reduces the read disturb effect by eliminating the hole traps in oxide and restoring the shortened channel induced by over erasure. Therefore, device scaling is achievable.
To achieve the above-mentioned object, the present invention provides a method of an erase scheme for a non-volatile memory cell. The non-volatile memory cell includes a substrate, source, drain with a channel region and a gate above the channel region separated by nonconducting charge-trapping material sandwiched between first and second silicon dioxide layers. The method includes the following steps. First, hot hole erase is performed to inject hot holes into the nonconducting charge-trapping material to eliminate first electrons trapped in the nonconducting charge-trapping material and causing some holes to remain in the second silicon dioxide layer. Finally, soft anneal is performed to detrap the holes left in the second silicon dioxide layer or to inject second electrons to the second silicon dioxide layer to eliminate the holes left in the second silicon dioxide layer.


REFERENCES:
patent: 5768192 (1998-06-01), Eitan
patent: 6034896 (2000-03-01), Ranaweera et al.
patent: 6512696 (2003-01-01), Fan et al.
patent: 2003/0036250 (2003-02-01), Lin et al.

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