Static information storage and retrieval – Floating gate – Particular biasing
Patent
1996-06-12
1997-06-03
Clawson, Jr., Joseph E.
Static information storage and retrieval
Floating gate
Particular biasing
36512512, 36518519, 36518524, 3651853, 36518533, 365236, G11C 1606
Patent
active
056361629
ABSTRACT:
A procedure for erasing a Flash EPROM array (AR) includes applying a series of erase pulses to all of the subarrays (S1, S2, etc.) of a Flash EPROM array (AR) simultaneously. Between each erase pulse, the memory cells (10) of each sub array (S1, S2, etc.) are simultaneously checked one row at a time and one column position at a time, to see whether or not any cell (10) is over-erased. If, at any time during the procedure a cell (10) is found to be over-erased, the over-erased condition is corrected and the erase procedure continues, but with erase pulses applied only to those subarrays (S1, S2, etc.) having non-erased memory cells (10) as in prior-art subarray erase procedures. Under almost all circumstances, the procedure of this invention decreases over-all erase time.
REFERENCES:
patent: 5568439 (1996-10-01), Harari
Coffman Tim M.
Lin Sung-Wei
Truong Phat C.
Clawson Jr. Joseph E.
Donaldson Richard L.
Heiting Leo N.
Lindgren Theodore D.
Texas Instruments Incorporated
LandOfFree
Erase procedure does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Erase procedure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Erase procedure will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-396719