Erase of a memory having a non-conductive storage medium

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185260

Reexamination Certificate

active

06898129

ABSTRACT:
A non volatile memory includes a plurality of transistors having a non conductive storage medium. The transistors are erased by injecting holes into the storage medium from both the source edge region and drain edge region of the transistor. In one example, the storage medium is made from silicon nitride isolated from the underlying substrate and overlying gate by silicon dioxide. The injection of holes in the storage medium generates two hole distributions having overlapping portions. The combined distribution of the overlapping portions is above at least a level of the highest concentration of program charge in the overlap region of the storage medium. In one example, the transistors are programmed by hot carrier injection. In some examples, the sources of groups of transistors of the memory are decoded.

REFERENCES:
patent: 5892714 (1999-04-01), Choi
patent: 6011725 (2000-01-01), Eitan
patent: 6356482 (2002-03-01), Derhacobian et al.
patent: 20030080370 (2003-05-01), Harari et al.
Fujiwara et al., “High Speed Program/Erase Sub 100 nm MONOS Memory Cell,” Advanced Devices R&D Laboratories, LSI, SNC, Sony Corporation, pp. 75-77.

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