Erase method to reduce erase time and to prevent over-erase

Details Erase method to reduce erase time and to prevent over-erase Erase method to reduce erase time and to prevent over-erase

2007-10-02

2007-10-02

Phung, Anh (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185220

Reexamination Certificate

active

11297085

ABSTRACT:
An erase method used in an array of flash memory cells arranged in a plurality of sectors provides each sector with an erase flag. The erase flag of sectors to be erased are set to a first value. The memory cells are sequentially verified from a first sector to a last sector whose flag is set to the first value and for each sector from a first address to a last address. When verification fails and the number of the same-cell-verifications is less than a predetermined number, the method applies an erase pulse and verifies the memory call at the same memory address again. When verification fails and the number of same-cell-verifications reaches the predetermined number, the remaining sectors whose flag is set to the first value are verified. When each memory cell of a sector to be erased passes verification, the erase flag of the sector is set to a second value. When the flag of each sector to be erased is set to the second value, the erase operation is terminated.

REFERENCES:
patent: 5414664 (1995-05-01), Lin et al.
patent: 6529413 (2003-03-01), Lee et al.
patent: 6639844 (2003-10-01), Liu et al.
patent: 6903980 (2005-06-01), Miki et al.

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