Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-07-17
2004-03-23
Mai, Son (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185290, C365S185330
Reexamination Certificate
active
06711062
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention generally relates to a method used in semiconductor memory manufacturing and, more particularly, to a method of erasing memory reference cells in a split gate flash electrically erasable programmable read only memory (EEPROM) in the fabrication of integrated circuits (ICs).
(2) Description of Prior Art
Electrically erasable EEPROMs often referred to as “Flash” EEPROM, have emerged as an important non-volatile memory. Having the same cell density as standard EPROMs, they have the advantage over EPROMs that they need not be exposed to ultraviolet (UV) light to be erased. This is also an advantage in that standard IC packages can be used for these devices whereas standard EPROMs require a special package allowing the IC die to be exposed to UV light.
In a standard Flash EEPROM, a plurality of flash memory cells are arranged in an array of rows and columns. Refer now to
FIG. 1
showing a typical flash memory cell device. Each cell
10
is composed of a p-type substrate
12
and separate n-type source
14
and drain
16
regions formed on the substrate
12
. A p-type channel region
18
in the substrate
12
separates the source
14
and drain
16
. A floating gate
20
, electrically isolated from and positioned over the channel region
18
, is separated from the substrate
12
by a thin dielectric layer
22
. A control gate
24
is separated from the floating gate
20
by a second dielectric layer
26
.
To program the flash EEPROM cell, the drain and control gate are raised to voltages above the voltage applied to the source region. For example, the drain voltage (V
D
) and control gate voltage (V
CG
) are set to 5.5 V and 9 V above the source voltage, respectively. This produces hot electrons, which are transferred across the thin dielectric layer, trapping them on the floating gate. The control gate voltage threshold is the minimum voltage that must be applied to the control gate in order to affect conduction between the source and drain. This injection of hot electrons has the effect of raising the control gate threshold by about two to four volts.
To erase a flash EEPROM cell, the source voltage (V
s
) is set to a positive voltage and the control gate voltage (V
CG
) is set to a negative voltage (e.g. 5 V and −8 V, respectively) while the drain floats. An electric field forms between the source and floating gate thereby removing the negative charge on the floating gate by Fowler-Nordheim tunneling.
In order to determine the programming state of a cell, the magnitude of the cell read current is measured. This is accomplished as shown in
FIG. 2. A
reference current source
40
set to approximately 25 uA is connected to ground potential. The memory cell
42
being examined is connected with the drain wired to a fixed positive voltage between about 1 to 2 volts, for example. The source of the memory cell
42
is connected to the ungrounded terminal of the current source
40
. The control gate voltage (V
CG
) is set to approximately 5 V. Under these read conditions, an unprogrammed memory cell
42
(storing a logic
1
) will have a drain current equal to that of the reference current source
40
and the output (cell source voltage) will be slightly less than the voltage applied to the drain (logic
1
). A programmed memory cell (logic
0
), having a higher threshold voltage, will conduct only leakage currents. This results in the output (cell source voltage) being very close to ground potential (logic
0
). Older memory technologies compared the memory cell current against a fixed current source. Because the current source circuitry differed from the memory cell circuitry, the current characteristics of the two limited the tolerance for variations in manufacturing process. More recent technologies and the memory circuit of the present invention use a “reference cell” identical to the standard memory cell to form the current source. This reference cell has been erased under the same conditions as a memory cell. Since the memory and reference cells are identical in geometry, their current characteristics will track regardless of manufacturing process variations. By comparing the memory cell current with the reference cell current, determination of the cell condition is simply achieved as described above.
In order to maintain the proper state for the reference cells, they must be periodically erased. A simple method would require that the user initiate a command to erase the reference cells; however this would require additional external circuitry and complexity to use the memory circuit. Another method would be to erase the reference cells simultaneously with each memory cell erasure. This, however, could cause high voltage overstressing resulting in damage to the decoder circuitry. Most flash EEPROM manufacturers erase the reference cells during a mass erase (when the entire array is erased).This results in high voltage stress equal to (in the case of mass erase) or less than (in the case of page erase) that of the normal memory array. Other approaches related to improving Flash EEPROMs exist. U.S. Pat. No. 6,122,198 to Haddad et al. teaches a method for guaranteeing that an erased cell threshold voltage in a two bit per cell flash EEPROM falls within prescribed limits. This is accomplished by testing for both over and under erase conditions until all cells pass satisfactorily. U.S. Pat. No. 5,675,537 to Bill et al. teaches a method where overerasure of memory cells in a Flash EPROM is prevented by halting erasure once a prescribed cell threshold is reached. U.S. Pat. No. 5,801,985 to Roohparvar et al. teaches a method where non-volatile memory is used to set memory system parameters such as threshold, word length, and addressing scheme. U.S. Pat. No. 6,073,204 to Lakhani et al teaches a method using a single memory controller connected to several memory devices using common bus architecture to optimize memory performance.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide a method that erases the reference cells in a Flash EEPROM memory.
Another object of the present invention is to provide a method that erases the reference cells in a Flash EEPROM memory upon application of power to the memory device.
Another object of the present invention is to provide a method that erases the reference cells in a Flash EEPROM memory upon application of power to the memory device without requiring the application of external signals.
Another object of the present invention is to provide a method that erases the reference cells in a Flash EEPROM memory upon application of power to the memory device without requiring the application of external signals, thereby reducing the high voltage stress on the reference cell decoder circuitry.
These objects are achieved by using a method where a pulse is generated upon application of power to the Flash EEPROM memory that initiates the erasure of each of the reference cells.
REFERENCES:
patent: 5675537 (1997-10-01), Bill et al.
patent: 5784314 (1998-07-01), Sali et al.
patent: 5801985 (1998-09-01), Roohparvar et al.
patent: 6073204 (2000-06-01), Lakhani et al.
patent: 6122198 (2000-09-01), Haddad et al.
patent: 6278634 (2001-08-01), Ra
patent: 6317362 (2001-11-01), Nomura et al.
Ackerman Stephen B.
Pike Rosemary L. S.
Saile George O.
Taiwan Semiconductor Manufacturing Company
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