Erase method in flash memory device

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185280

Reexamination Certificate

active

11024628

ABSTRACT:
An erase method in a flash memory device by which over-erase of the flash memory device is prevented. The method includes applying an electric field to a structure between the control gate and the semiconductor substrate by applying negative and positive voltages to the control gate and the semiconductor substrate, respectively. The method further includes weakening an intensity of the electric field applied to the tunnel oxide layer according to a progress of an erase time, and simultaneously, relatively strengthening an intensity of the electric field applied to the first and second block oxide layers to constantly maintain a prescribed quantity of electrons on a conduction band of the floating gate.

REFERENCES:
patent: 5742541 (1998-04-01), Tanigami et al.
patent: 6160740 (2000-12-01), Cleveland
patent: 6847557 (2005-01-01), Yang

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