Static information storage and retrieval – Floating gate – Particular biasing
Patent
1996-08-22
1997-10-07
Nelms, David C.
Static information storage and retrieval
Floating gate
Particular biasing
36518529, 3651853, G11C 1134
Patent
active
056755376
ABSTRACT:
An improved erasing structure for performing a programming back operation and a concurrent verify operation subsequent to application of an erasing pulse in an array of multiple bits-per-cell flash EEPROM memory cells is provided. A memory core array (12) includes a plurality of memory cells and an erase verify reference cell array for generating an upper erased state threshold voltage level. A pre-charge circuit (36a) is used to pre-charge all the array bit lines to a predetermined potential prior to a programming back operation. A reference generator circuit (134) is used for generating a reference output voltage corresponding to a lower erased state threshold voltage level. A switching circuit (P1, N1) is used to selectively disconnect a program current source of approximately 5 .mu.A from the selected certain ones of the columns of array bit lines containing the selected memory core cells which have been correctly programmed back. A sense logic circuit (26, 27) continuously compares a potential on one of the selected bit lines and the reference output voltage corresponding to the lower erase threshold voltage level. The sensing logic circuit generates a logic signal which is switched to a low logic level when the potential on the selected bit line falls below the bit line voltage corresponding to the lower erased state threshold voltage level. The switching circuit is responsive to the low logic level for disconnecting the programming current source so as to inhibit further programming back of the selected memory core cells.
Bill Colin Stewart
Gutala Ravi Prakash
Su Jonathan Shichang
Advanced Micro Devices , Inc.
Chin Davis
Nelms David C.
Niranjan F.
LandOfFree
Erase method for page mode multiple bits-per-cell flash EEPROM does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Erase method for page mode multiple bits-per-cell flash EEPROM, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Erase method for page mode multiple bits-per-cell flash EEPROM will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2362676