Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-07-05
2002-11-19
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185220, C365S185170
Reexamination Certificate
active
06483752
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an erase method for nonvolatile semiconductor memory devices, and in particular, to an erase method for a nonvolatile semiconductor memory device in which threshold voltages of memory cells in an erased state are lower than threshold voltages of memory cells in a written state.
One of most widely used flash memories is a flash memory of ETOX (a registered trademark of Intel Corp.) type, a memory cell of which has a basic structure as shown in FIG.
11
. The memory cell of this basic structure has a source
12
and a drain
13
formed on a surface of a substrate (well)
11
. Above a channel region
14
located between the source and the drain, a floating gate FG is formed with the interposition of a tunnel oxide film
15
, and a control gate CG is further formed with the interposition of an interlayer insulation film
16
.
The principle of operation of the flash memory of ETOX type will be described. As shown in Table 1, during a write (program) operation, there are applied a voltage Vpp (10 V, for example) to the control gate CG, a reference voltage Vss (0 V, for example) to the source
12
, and a voltage of 6 V to the drain
13
. It is to be noted that the drain application voltage of “6 V/0 V” in Table 1 means the application of a voltage of 6 V to the drain of a selected memory cell and the application of a voltage of 0 V to the drain of a non-selected memory cell.
TABLE 1
Conventional Applied Voltages in Various Modes
Control
Gate
Drain
Source
Substrate
Write
10 V
6 V/0 V
0 V
0 V
(Program)
Erase
−9 V
Open
4 V
0 V
Read
5 V
1 V
0 V
0 V
With this arrangement, a large current flows through the channel region
14
of a memory cell as shown in
FIG. 12
, and channel hot electrons (CHE) are generated in a drain-side portion where the electric field is high. The generated electrons are injected into the floating gate FG, and the threshold voltage of the memory cell rises. The threshold voltage distribution of memory cells in the written state has a mean value of 5.0 V and a lower limit of 4.5 V. This is shown in FIG.
10
.
As shown in Table 1, during an erase operation, there are applied a voltage Vnn (−9 V, for example) to the control gate CG and a voltage Vpe (4 V, for example) to the source
12
. Then, as shown in
FIG. 13
, the drain
13
is opened to extract electrons at the source side, thereby lowering the threshold value of the memory cell (source side erase). The threshold voltage distribution of the memory cells in the erased state has an upper limit of 2.5 V and a lower limit of 0.5 V, as shown in FIG.
10
. During this erase operation, a BTBT (Band To Band Tunneling) current flows, and hot holes and hot electrons are generated at the same time. Among these, the hot electrons flow to the drain
13
, whereas the hot holes are pulled to the tunnel oxide film side and trapped in the tunnel oxide film. It is generally said that this phenomenon degrades the reliability.
As shown in Table 1, during a read (readout) operation of a memory cell, there are applied a voltage of 1 V to the drain
13
and a voltage of 5 V to the control gate CG. When the memory cell is in the erased state with a low threshold voltage, a current flows through the memory cell, and this state is determined to be “1”. When the memory cell is in the written state with a high threshold voltage, no current flows through the memory cell, and this state is determined to be “0”.
The aforementioned operating method has a problem that the reliability of the memory cell is deteriorated by the band to band tunneling current generated through the source side erase operation. As a measure for solving this problem, there is a method of executing “channel erase” by which no band to band tunneling current is generated. In order to execute this channel erase operation, there is employed a memory cell having a triple well structure in which an N-well is arranged outside a P-well, as shown in FIG.
16
. In the memory cell of this triple well structure, an N-well
22
is formed on the surface of a P-type substrate
21
, and a P-well
23
is formed in this N-well
22
. Further, a source
24
and a drain
25
are formed at a surface of the P-well
23
. A floating gate FG is formed on a channel region
26
located between the source and the drain via a tunnel oxide film (not shown), and a control gate CG is further formed via an interlayer insulation film (not shown).
Table 2 shows applied voltages in each mode for the memory cell of the triple well structure. As shown in Table 2, the write operation and the read operation for the memory cell of this triple well structure are executed on the same voltage application conditions as those for the memory cell of the aforementioned basic structure (FIG.
11
).
FIG. 17
shows the write operation by channel hot electrons. In this case, in addition to the voltage application conditions of
FIG. 12
there are further applied a voltage of 3 V to the N-well
22
and a voltage of 0 V to the substrate
21
and the P-well
23
.
TABLE 2
Conventional Applied Voltages in Various Modes
Control
Gate
Drain
Source
P-well
Write
10 V
6 V/0 V
0 V
0 V
(Program)
Erase
−9 V
Open
7 V
7 V
Read
5 V
1 V
0 V
0 V
When executing channel erase in the memory cell of the triple well structure, as shown in
FIG. 18
, there are applied a voltage Vnn (−9 V, for example) to the control gate CG (word line) and a voltage Vesc (+7 V, for example) to the source
24
and the N-well
22
. By this operation, an intense electric field is applied to the tunnel oxide film located between the channel region
26
and the floating gate FG, and electrons are extracted from the floating gate FG to the channel region
26
by the Fowler-Nordheim tunneling phenomenon, with the result that the threshold voltage lowers. At this time, the potential of the source
24
and the potential of the P-well
23
are equal to each other. Therefore, no electric field is concentrated on the boundary between the source
24
and the P-well
23
, and the band to band tunneling current is not generated. Consequently, hot holes are neither generated nor trapped, and the reliability of the memory cell is improved.
FIG. 14
shows an array structure of the flash memory that employs the aforementioned memory cells. As is apparent from the figure, the array structure is a NOR type array structure. When a threshold voltage distribution as shown in
FIG. 10
is provided in the above array structure, there is a problem as follows.
Basically, the threshold voltage distribution after the channel erase becomes a distribution similar to that labeled erased state in
FIG. 10. A
case where characteristic change occurs after repeated erase and write operations will be discussed. For example, assume that the threshold voltage of a memory cell M
127
bearing the mark o in
FIG. 14
was subjected to excessive erasure and made to have a negative threshold voltage (−0.3 V, for example), and that a memory cell M
01
bearing the mark &Dgr; was put into a written state (for example, the threshold voltage was set to 4.5 V). In this case, when reading the data of the memory cell M
01
bearing the mark &Dgr;, no current flows since the memory cell M
01
bearing the mark &Dgr; has a very high threshold voltage of not lower than 4.5 V. However, since the threshold voltage of the memory cell M
127
bearing the mark o has a negative value, a current flows even in a non-selected state, i.e., even when a word line WL
127
has a voltage of 0 V. Therefore, if a current flowing through a bit line BL
0
is detected by applying a voltage of 1 V to the bit line BL
0
, then the data of the memory cell M
01
bearing the mark &Dgr; is determined to be “1” (a state in which the threshold voltage is low), which is a misread. As understood from this fact, the NOR (non-disjunction) type flash memory is not permitted to have a negative threshold voltage in the array.
An erase algorithm as shown in
FIG. 15
is used as a method for solving the aforementioned problem in the flash memory (se
Hoang Huan
Morrison & Foerster / LLP
Sharp Kabushiki Kaisha
LandOfFree
Erase method for nonvolatile semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Erase method for nonvolatile semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Erase method for nonvolatile semiconductor memory device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2973699