Erase inhibit in non-volatile memories

Details Erase inhibit in non-volatile memories Erase inhibit in non-volatile memories

2005-10-25

2005-10-25

Phung, Anh (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S185010, C365S185140, C365S185250, C365S185290

Reexamination Certificate

active

06958936

ABSTRACT:
The present invention presents a non-volatile memory and method for its operation that can reduce the amount of disturb in non-selected cells during an erase process. For a set of storage elements formed over a common well structure, all word-lines are initially charged with the same high voltage erase signal that charges the well to insure there is no net voltage difference between the well and word-lines. The selected word-lines are then discharged to ground while the non-selected word-lines and the well are maintained at the high voltage. According to another aspect of the present invention, this can be accomplished without increasing any pitch area circuit or adding new wires in the memory array, and at minimal additional peripheral area. Advantages include less potential erase disturb in the non-selected storage elements and a tighter erase distribution for the selected elements.

REFERENCES:
patent: 6373746 (2002-04-01), Takeuchi et al.
patent: 6442080 (2002-08-01), Tanzawa et al.
patent: 6522580 (2003-02-01), Chen et al.
patent: 2002/0167844 (2002-11-01), Han et al.
patent: 1 271 553 (2003-01-01), None
International Search Report, International Application No. PCT/US2004/031082, mailed Jan. 28, 2005, 3 pages.
Written Opinion of the International Search Authority, International Application No. PCT/US2004/031082, mailed Jan. 28, 2005, 6 pages.

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