Erase degradation reduction in non-volatile memory

Details Erase degradation reduction in non-volatile memory Erase degradation reduction in non-volatile memory

2008-03-31

2010-10-19

Dinh, Son (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185180, C365S185190, C365S185270

Reexamination Certificate

active

07817478

ABSTRACT:
Methods for erasing a memory device and memory systems are provided, such as those including a non-volatile memory device is erased by using an intermediate erase step prior to a normal erase step. The intermediate erase step is comprised of an erase pulse voltage, applied to the semiconductor well of the selected memory block of memory cells, while edge rows of memory cells are biased at a low positive voltage (e.g., 0.8-2V). An erase verify operation is then performed. If the selected memory block is not erased, a normal memory erase step is then performed in which the same erase pulse voltage is used but all of the rows are biased at ground potential as in a normal erase step. If the memory block is still fails the erase verify operation, the erase pulse voltage is increased and the process repeated.

REFERENCES:
patent: 7196932 (2007-03-01), Takeuchi et al.
patent: 7327604 (2008-02-01), Miwa et al.
patent: 7349257 (2008-03-01), Lee et al.

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