Erase cycle counter usage in a memory device

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C365S185290

Reexamination Certificate

active

08036035

ABSTRACT:
Memory devices and methods are disclosed to facilitate adjustment of program voltages applied during a program operation based upon erase operation cycle counter values stored in the memory device. In one such embodiment, an erase cycle counter is maintained for each block of a memory device and is stored in the associated block of memory. Programming voltage levels utilized during program operations of memory cells are determined, at least in part, based upon the value of the erase cycle counter stored in a memory block undergoing a programming operation, for example.

REFERENCES:
patent: 7679961 (2010-03-01), Lee et al.
patent: 2007/0245068 (2007-10-01), Yero
patent: 2008/0266970 (2008-10-01), Lee et al.
patent: 2009/0052269 (2009-02-01), Moschiano et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Erase cycle counter usage in a memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Erase cycle counter usage in a memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Erase cycle counter usage in a memory device will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4260471

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.